Timing Messages

Report Title Timing Analysis Report
Design File C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\impl\gwsynthesis\camera_hdmi.vg
Physical Constraints File C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\dk_video.cst
Timing Constraint File C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\dk_video.sdc
Version V1.9.8.09 Education
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Wed Jan 03 23:33:34 2024
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 4588
Numbers of Endpoints Analyzed 2986
Numbers of Falling Endpoints 33
Numbers of Setup Violated Endpoints 713
Numbers of Hold Violated Endpoints 2

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
I_clk Base 37.037 27.000 0.000 18.518 I_clk
serial_clk Base 2.694 371.195 0.000 1.347 serial_clk
pix_clk Base 13.468 74.250 0.000 6.734 pix_clk
ch0_vfb_clk_in Base 20.000 50.000 0.000 10.000 ch0_vfb_clk_in_s0/F
GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk Generated 6.289 159.000 0.000 3.145 I_clk_ibuf/I I_clk GW_PLLVR_inst/pllvr_inst/CLKOUT
GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk Generated 6.289 159.000 0.000 3.145 I_clk_ibuf/I I_clk GW_PLLVR_inst/pllvr_inst/CLKOUTP
GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk Generated 12.579 79.500 0.000 6.289 I_clk_ibuf/I I_clk GW_PLLVR_inst/pllvr_inst/CLKOUTD
GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk Generated 18.868 53.000 0.000 9.434 I_clk_ibuf/I I_clk GW_PLLVR_inst/pllvr_inst/CLKOUTD3
TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk Generated 2.694 371.250 0.000 1.347 I_clk_ibuf/I I_clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTP
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk Generated 80.808 12.375 0.000 40.404 I_clk_ibuf/I I_clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk Generated 8.081 123.750 0.000 4.040 I_clk_ibuf/I I_clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3
HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Generated 12.579 79.500 0.000 6.289 GW_PLLVR_inst/pllvr_inst/CLKOUT GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 27.000(MHz) 118.114(MHz) 5 TOP
2 pix_clk 74.250(MHz) 66.606(MHz) 12 TOP
3 ch0_vfb_clk_in 50.000(MHz) 93.830(MHz) 7 TOP
4 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk 12.375(MHz) 79.776(MHz) 5 TOP
5 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk 79.500(MHz) 71.041(MHz) 9 TOP

No timing paths to get frequency of serial_clk!

No timing paths to get frequency of GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk!

No timing paths to get frequency of TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
I_clk Setup 0.000 0
I_clk Hold 0.000 0
serial_clk Setup 0.000 0
serial_clk Hold 0.000 0
pix_clk Setup -6.168 11
pix_clk Hold 0.000 0
ch0_vfb_clk_in Setup 0.000 0
ch0_vfb_clk_in Hold 0.000 0
GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk Setup 0.000 0
GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk Hold 0.000 0
GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk Setup 0.000 0
GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk Hold 0.000 0
GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk Setup 0.000 0
GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk Hold 0.000 0
GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk Setup 0.000 0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk Hold 0.000 0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk Setup 0.000 0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk Hold 0.000 0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk Hold 0.000 0
HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Setup -1.776 2
HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -8.036 key_flag_inst/key_flag_s1/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/D I_clk:[R] ch0_vfb_clk_in:[R] 0.001 1.397 6.210
2 -7.950 key_flag_inst/key_flag_s1/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1/D I_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.699 1.771 6.448
3 -7.629 key_flag_inst/key_flag_s1/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0/D I_clk:[R] ch0_vfb_clk_in:[R] 0.001 1.397 5.803
4 -7.629 key_flag_inst/key_flag_s1/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/D I_clk:[R] ch0_vfb_clk_in:[R] 0.001 1.397 5.803
5 -7.626 key_flag_inst/key_flag_s1/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/D I_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.699 1.771 6.124
6 -5.688 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[8]/D GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 6.289 1.122 10.425
7 -5.631 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[7]/D GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 6.289 1.122 10.368
8 -5.574 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[6]/D GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 6.289 1.122 10.311
9 -5.533 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync[4]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CE I_clk:[R] GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F] 0.349 0.897 4.702
10 -5.517 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[5]/D GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 6.289 1.122 10.254
11 -5.460 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[4]/D GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 6.289 1.122 10.197
12 -5.403 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[3]/D GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 6.289 1.122 10.140
13 -5.346 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[2]/D GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 6.289 1.122 10.083
14 -5.289 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[1]/D GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 6.289 1.122 10.026
15 -4.465 syn_gen_inst/O_vs_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.127 -0.330 4.492
16 -3.646 syn_gen_inst/O_vs_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.127 -0.330 3.673
17 -3.054 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_10_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_10_s0/D ch0_vfb_clk_in:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.125 0.374 2.376
18 -3.005 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_8_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_8_s0/D HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] pix_clk:[R] 0.127 0.330 2.372
19 -2.833 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_10_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_10_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.127 -0.330 2.861
20 -2.829 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_4_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_4_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.127 -0.330 2.856
21 -2.736 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_1_s0/D ch0_vfb_clk_in:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.125 0.374 2.058
22 -2.592 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[0]/D GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 6.289 1.122 7.329
23 -2.566 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_0_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0/D ch0_vfb_clk_in:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.125 0.374 1.887
24 -2.566 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_2_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_2_s0/D ch0_vfb_clk_in:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.125 0.374 1.887
25 -2.566 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_3_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_3_s0/D ch0_vfb_clk_in:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.125 0.374 1.887

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -0.334 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/CALIB HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 0.927
2 -0.334 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4/CALIB HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 0.927
3 0.156 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/CALIB HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.416
4 0.156 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/CALIB HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.416
5 0.432 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/CALIB HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.693
6 0.438 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/CALIB HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.699
7 0.438 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/CALIB HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.699
8 0.480 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/CALIB HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R] 0.000 -1.230 1.740
9 0.556 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state_Z[10]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep1/CE HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.571
10 0.556 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state_Z[10]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep2/CE HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.571
11 0.562 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib_done[0]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CE HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 0.000 0.577
12 0.576 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_0_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_0_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 -0.330 0.937
13 0.576 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_2_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_2_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 -0.330 0.937
14 0.576 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_5_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_5_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 -0.330 0.937
15 0.576 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_6_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_6_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 -0.330 0.937
16 0.576 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_8_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_8_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 -0.330 0.937
17 0.595 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_1_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_1_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 -0.330 0.955
18 0.595 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_3_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_3_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 -0.330 0.955
19 0.595 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_7_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_7_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 -0.330 0.955
20 0.595 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_9_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_9_s0/D pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R] 0.000 -0.330 0.955
21 0.708 u_OV2640_Controller/I2C/divider_0_s2/Q u_OV2640_Controller/I2C/divider_0_s2/D TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R] TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.708
22 0.708 u_OV2640_Controller/I2C/divider_3_s1/Q u_OV2640_Controller/I2C/divider_3_s1/D TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R] TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.708
23 0.708 u_OV2640_Controller/I2C/divider_5_s1/Q u_OV2640_Controller/I2C/divider_5_s1/D TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R] TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.708
24 0.708 u_OV2640_Controller/I2C/divider_6_s1/Q u_OV2640_Controller/I2C/divider_6_s1/D TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R] TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.708
25 0.708 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_fast_Z[1]/Q HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_fast_Z[1]/D I_clk:[R] I_clk:[R] 0.000 0.000 0.708

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 -5.792 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk/RESET I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
2 -5.792 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/RESET I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
3 -5.792 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g/RESET I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
4 -5.792 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r/RESET I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
5 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0/PRESET I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
6 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
7 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
8 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
9 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
10 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
11 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
12 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
13 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
14 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
15 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
16 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
17 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
18 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
19 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
20 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
21 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
22 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0/PRESET I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
23 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
24 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982
25 -5.790 u_Reset_Sync/reset_cnt_3_s0/Q DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0/CLEAR I_clk:[R] pix_clk:[R] 3.367 2.101 6.982

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.869 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s1/PRESET pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F] -0.064 -0.338 1.189
2 0.869 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s1/PRESET pix_clk:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F] -0.064 -0.338 1.189
3 1.001 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1/PRESET ch0_vfb_clk_in:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F] -0.001 0.162 0.883
4 1.001 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/Q Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s1/PRESET ch0_vfb_clk_in:[R] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F] -0.001 0.162 0.883
5 1.892 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_22_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.907
6 1.892 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_23_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.907
7 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_0_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
8 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_1_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
9 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_2_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
10 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_6_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
11 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_9_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
12 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_10_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
13 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_11_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
14 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_12_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
15 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_13_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
16 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_14_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
17 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_15_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
18 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_16_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
19 1.898 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_19_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.913
20 1.904 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_3_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.919
21 1.904 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_17_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.919
22 1.904 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_18_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.919
23 1.904 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_21_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 1.919
24 2.160 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_20_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 2.175
25 2.160 u_Reset_Sync/reset_cnt_2_s0/Q run_cnt_24_s0/CLEAR I_clk:[R] I_clk:[R] 0.000 0.000 2.175

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0
2 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0
3 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_12_s1
4 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_5_s0
5 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0
6 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq2_wptr_3_s0
7 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_9_s0
8 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_7_s0
9 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_6_s0
10 4.965 6.215 1.250 Low Pulse Width HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].id_reg[16]

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -8.036
Data Arrival Time 1008.552
Data Required Time 1000.516
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0
Launch Clk I_clk:[R]
Latch Clk ch0_vfb_clk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
999.999 999.999 active clock edge time
999.999 0.000 I_clk
999.999 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
1000.981 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
1002.342 1.361 tNET RR 1 R17C19[2][B] key_flag_inst/key_flag_s1/CLK
1002.800 0.458 tC2Q RF 4 R17C19[2][B] key_flag_inst/key_flag_s1/Q
1004.744 1.943 tNET FF 1 R2C18[3][A] ch0_vfb_vs_in_s1/I0
1005.566 0.822 tINS FF 5 R2C18[3][A] ch0_vfb_vs_in_s1/F
1007.520 1.955 tNET FF 1 R16C19[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n16_s1/I0
1008.552 1.032 tINS FF 1 R16C19[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n16_s1/F
1008.552 0.000 tNET FF 1 R16C19[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1000.000 1000.000 active clock edge time
1000.000 0.000 ch0_vfb_clk_in
1000.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1000.946 0.946 tNET RR 1 R16C19[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/CLK
1000.916 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0
1000.516 -0.400 tSu 1 R16C19[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0

Path Statistics:

Clock Skew -1.397
Setup Relationship 0.001
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 1.854, 29.854%; route: 3.898, 62.765%; tC2Q: 0.458, 7.380%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.946, 100.000%

Path2

Path Summary:

Slack -7.950
Data Arrival Time 45.828
Data Required Time 37.878
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1
Launch Clk I_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R17C19[2][B] key_flag_inst/key_flag_s1/CLK
39.838 0.458 tC2Q RF 4 R17C19[2][B] key_flag_inst/key_flag_s1/Q
41.782 1.943 tNET FF 1 R2C18[3][A] ch0_vfb_vs_in_s1/I0
42.604 0.822 tINS FF 5 R2C18[3][A] ch0_vfb_vs_in_s1/F
45.828 3.224 tNET FF 1 R13C24[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
38.308 0.242 tNET RR 1 R13C24[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1/CLK
38.278 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1
37.878 -0.400 tSu 1 R13C24[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.822, 12.749%; route: 5.167, 80.143%; tC2Q: 0.458, 7.109%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack -7.629
Data Arrival Time 1008.145
Data Required Time 1000.516
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0
Launch Clk I_clk:[R]
Latch Clk ch0_vfb_clk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
999.999 999.999 active clock edge time
999.999 0.000 I_clk
999.999 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
1000.981 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
1002.342 1.361 tNET RR 1 R17C19[2][B] key_flag_inst/key_flag_s1/CLK
1002.800 0.458 tC2Q RF 4 R17C19[2][B] key_flag_inst/key_flag_s1/Q
1004.744 1.943 tNET FF 1 R2C18[3][A] ch0_vfb_vs_in_s1/I0
1005.566 0.822 tINS FF 5 R2C18[3][A] ch0_vfb_vs_in_s1/F
1008.145 2.580 tNET FF 1 R15C18[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1000.000 1000.000 active clock edge time
1000.000 0.000 ch0_vfb_clk_in
1000.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1000.946 0.946 tNET RR 1 R15C18[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0/CLK
1000.916 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0
1000.516 -0.400 tSu 1 R15C18[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0

Path Statistics:

Clock Skew -1.397
Setup Relationship 0.001
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.822, 14.165%; route: 4.523, 77.937%; tC2Q: 0.458, 7.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.946, 100.000%

Path4

Path Summary:

Slack -7.629
Data Arrival Time 1008.145
Data Required Time 1000.516
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
Launch Clk I_clk:[R]
Latch Clk ch0_vfb_clk_in:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
999.999 999.999 active clock edge time
999.999 0.000 I_clk
999.999 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
1000.981 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
1002.342 1.361 tNET RR 1 R17C19[2][B] key_flag_inst/key_flag_s1/CLK
1002.800 0.458 tC2Q RF 4 R17C19[2][B] key_flag_inst/key_flag_s1/Q
1004.744 1.943 tNET FF 1 R2C18[3][A] ch0_vfb_vs_in_s1/I0
1005.566 0.822 tINS FF 5 R2C18[3][A] ch0_vfb_vs_in_s1/F
1007.519 1.954 tNET FF 1 R15C18[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_rising_s0/I1
1008.145 0.626 tINS FF 1 R15C18[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_rising_s0/F
1008.145 0.000 tNET FF 1 R15C18[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1000.000 1000.000 active clock edge time
1000.000 0.000 ch0_vfb_clk_in
1000.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1000.946 0.946 tNET RR 1 R15C18[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/CLK
1000.916 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
1000.516 -0.400 tSu 1 R15C18[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0

Path Statistics:

Clock Skew -1.397
Setup Relationship 0.001
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 1.448, 24.952%; route: 3.897, 67.150%; tC2Q: 0.458, 7.898%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.946, 100.000%

Path5

Path Summary:

Slack -7.626
Data Arrival Time 45.504
Data Required Time 37.878
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0
Launch Clk I_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R17C19[2][B] key_flag_inst/key_flag_s1/CLK
39.838 0.458 tC2Q RF 4 R17C19[2][B] key_flag_inst/key_flag_s1/Q
41.782 1.943 tNET FF 1 R2C18[3][A] ch0_vfb_vs_in_s1/I0
42.604 0.822 tINS FF 5 R2C18[3][A] ch0_vfb_vs_in_s1/F
45.504 2.901 tNET FF 1 R13C21[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.736 37.736 active clock edge time
37.736 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
38.066 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
38.308 0.242 tNET RR 1 R13C21[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/CLK
38.278 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0
37.878 -0.400 tSu 1 R13C21[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0

Path Statistics:

Clock Skew -1.771
Setup Relationship 0.699
Logic Level 2
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.822, 13.422%; route: 4.844, 79.094%; tC2Q: 0.458, 7.484%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack -5.688
Data Arrival Time 18.408
Data Required Time 12.721
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[8]
Launch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.289 6.289 active clock edge time
6.289 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
7.736 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
7.736 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.984 0.248 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.099 0.115 tNET RR 8 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
8.665 0.566 tINS RF 2 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[0]
12.402 3.737 tNET FF 2 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
13.360 0.958 tINS FF 1 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
13.360 0.000 tNET FF 2 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
13.417 0.057 tINS FF 1 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
13.417 0.000 tNET FF 2 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
13.474 0.057 tINS FF 1 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
13.474 0.000 tNET FF 2 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
13.531 0.057 tINS FF 1 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
13.531 0.000 tNET FF 2 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
13.588 0.057 tINS FF 1 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
13.588 0.000 tNET FF 2 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
13.645 0.057 tINS FF 1 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
13.645 0.000 tNET FF 2 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
13.702 0.057 tINS FF 1 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
13.702 0.000 tNET FF 2 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
13.759 0.057 tINS FF 1 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
14.327 0.568 tNET FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/I1
15.426 1.099 tINS FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/F
16.896 1.470 tNET FF 2 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/I1
17.446 0.550 tINS FR 1 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
17.446 0.000 tNET RR 2 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
17.503 0.057 tINS RF 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
17.503 0.000 tNET FF 2 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
17.560 0.057 tINS FF 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
17.560 0.000 tNET FF 2 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
17.617 0.057 tINS FF 1 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
17.617 0.000 tNET FF 2 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
17.674 0.057 tINS FF 1 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/COUT
17.674 0.000 tNET FF 2 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_5_0/CIN
17.731 0.057 tINS FF 1 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_5_0/COUT
17.731 0.000 tNET FF 2 R18C13[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_6_0/CIN
17.788 0.057 tINS FF 1 R18C13[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_6_0/COUT
17.788 0.000 tNET FF 2 R18C13[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_7_0/CIN
17.845 0.057 tINS FF 1 R18C13[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_7_0/COUT
17.845 0.000 tNET FF 2 R18C13[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_s_8_0/CIN
18.408 0.563 tINS FF 1 R18C13[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_s_8_0/SUM
18.408 0.000 tNET FF 1 R18C13[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[8]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.579 12.579 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151 0.242 tNET RR 1 R18C13[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[8]/CLK
13.121 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[8]
12.721 -0.400 tSu 1 R18C13[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[8]

Path Statistics:

Clock Skew -1.122
Setup Relationship 6.289
Logic Level 8
Arrival Clock Path Delay cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 4.534, 43.495%; route: 5.776, 55.402%; tC2Q: 0.115, 1.103%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack -5.631
Data Arrival Time 18.351
Data Required Time 12.721
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[7]
Launch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.289 6.289 active clock edge time
6.289 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
7.736 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
7.736 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.984 0.248 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.099 0.115 tNET RR 8 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
8.665 0.566 tINS RF 2 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[0]
12.402 3.737 tNET FF 2 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
13.360 0.958 tINS FF 1 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
13.360 0.000 tNET FF 2 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
13.417 0.057 tINS FF 1 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
13.417 0.000 tNET FF 2 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
13.474 0.057 tINS FF 1 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
13.474 0.000 tNET FF 2 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
13.531 0.057 tINS FF 1 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
13.531 0.000 tNET FF 2 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
13.588 0.057 tINS FF 1 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
13.588 0.000 tNET FF 2 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
13.645 0.057 tINS FF 1 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
13.645 0.000 tNET FF 2 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
13.702 0.057 tINS FF 1 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
13.702 0.000 tNET FF 2 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
13.759 0.057 tINS FF 1 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
14.327 0.568 tNET FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/I1
15.426 1.099 tINS FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/F
16.896 1.470 tNET FF 2 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/I1
17.446 0.550 tINS FR 1 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
17.446 0.000 tNET RR 2 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
17.503 0.057 tINS RF 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
17.503 0.000 tNET FF 2 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
17.560 0.057 tINS FF 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
17.560 0.000 tNET FF 2 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
17.617 0.057 tINS FF 1 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
17.617 0.000 tNET FF 2 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
17.674 0.057 tINS FF 1 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/COUT
17.674 0.000 tNET FF 2 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_5_0/CIN
17.731 0.057 tINS FF 1 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_5_0/COUT
17.731 0.000 tNET FF 2 R18C13[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_6_0/CIN
17.788 0.057 tINS FF 1 R18C13[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_6_0/COUT
17.788 0.000 tNET FF 2 R18C13[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_7_0/CIN
18.351 0.563 tINS FF 1 R18C13[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_7_0/SUM
18.351 0.000 tNET FF 1 R18C13[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[7]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.579 12.579 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151 0.242 tNET RR 1 R18C13[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[7]/CLK
13.121 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[7]
12.721 -0.400 tSu 1 R18C13[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[7]

Path Statistics:

Clock Skew -1.122
Setup Relationship 6.289
Logic Level 8
Arrival Clock Path Delay cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 4.477, 43.185%; route: 5.776, 55.707%; tC2Q: 0.115, 1.109%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack -5.574
Data Arrival Time 18.294
Data Required Time 12.721
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[6]
Launch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.289 6.289 active clock edge time
6.289 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
7.736 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
7.736 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.984 0.248 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.099 0.115 tNET RR 8 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
8.665 0.566 tINS RF 2 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[0]
12.402 3.737 tNET FF 2 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
13.360 0.958 tINS FF 1 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
13.360 0.000 tNET FF 2 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
13.417 0.057 tINS FF 1 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
13.417 0.000 tNET FF 2 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
13.474 0.057 tINS FF 1 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
13.474 0.000 tNET FF 2 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
13.531 0.057 tINS FF 1 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
13.531 0.000 tNET FF 2 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
13.588 0.057 tINS FF 1 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
13.588 0.000 tNET FF 2 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
13.645 0.057 tINS FF 1 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
13.645 0.000 tNET FF 2 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
13.702 0.057 tINS FF 1 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
13.702 0.000 tNET FF 2 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
13.759 0.057 tINS FF 1 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
14.327 0.568 tNET FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/I1
15.426 1.099 tINS FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/F
16.896 1.470 tNET FF 2 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/I1
17.446 0.550 tINS FR 1 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
17.446 0.000 tNET RR 2 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
17.503 0.057 tINS RF 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
17.503 0.000 tNET FF 2 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
17.560 0.057 tINS FF 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
17.560 0.000 tNET FF 2 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
17.617 0.057 tINS FF 1 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
17.617 0.000 tNET FF 2 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
17.674 0.057 tINS FF 1 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/COUT
17.674 0.000 tNET FF 2 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_5_0/CIN
17.731 0.057 tINS FF 1 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_5_0/COUT
17.731 0.000 tNET FF 2 R18C13[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_6_0/CIN
18.294 0.563 tINS FF 1 R18C13[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_6_0/SUM
18.294 0.000 tNET FF 1 R18C13[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[6]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.579 12.579 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151 0.242 tNET RR 1 R18C13[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[6]/CLK
13.121 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[6]
12.721 -0.400 tSu 1 R18C13[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[6]

Path Statistics:

Clock Skew -1.122
Setup Relationship 6.289
Logic Level 8
Arrival Clock Path Delay cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 4.420, 42.870%; route: 5.776, 56.015%; tC2Q: 0.115, 1.115%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack -5.533
Data Arrival Time 192.230
Data Required Time 186.697
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync[4]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p
Launch Clk I_clk:[R]
Latch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
185.185 185.185 active clock edge time
185.185 0.000 I_clk
185.185 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
186.167 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
187.528 1.361 tNET RR 1 R5C10[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync[4]/CLK
187.986 0.458 tC2Q RF 11 R5C10[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync[4]/Q
192.230 4.243 tNET FF 1 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
185.534 185.534 active clock edge time
185.534 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
186.981 1.446 tCL FF 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
186.981 0.000 tNET FF 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
186.951 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p
186.697 -0.254 tSu 1 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p

Path Statistics:

Clock Skew -0.897
Setup Relationship 0.349
Logic Level 1
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 4.243, 90.252%; tC2Q: 0.458, 9.748%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path10

Path Summary:

Slack -5.517
Data Arrival Time 18.237
Data Required Time 12.721
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[5]
Launch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.289 6.289 active clock edge time
6.289 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
7.736 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
7.736 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.984 0.248 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.099 0.115 tNET RR 8 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
8.665 0.566 tINS RF 2 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[0]
12.402 3.737 tNET FF 2 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
13.360 0.958 tINS FF 1 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
13.360 0.000 tNET FF 2 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
13.417 0.057 tINS FF 1 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
13.417 0.000 tNET FF 2 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
13.474 0.057 tINS FF 1 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
13.474 0.000 tNET FF 2 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
13.531 0.057 tINS FF 1 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
13.531 0.000 tNET FF 2 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
13.588 0.057 tINS FF 1 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
13.588 0.000 tNET FF 2 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
13.645 0.057 tINS FF 1 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
13.645 0.000 tNET FF 2 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
13.702 0.057 tINS FF 1 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
13.702 0.000 tNET FF 2 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
13.759 0.057 tINS FF 1 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
14.327 0.568 tNET FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/I1
15.426 1.099 tINS FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/F
16.896 1.470 tNET FF 2 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/I1
17.446 0.550 tINS FR 1 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
17.446 0.000 tNET RR 2 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
17.503 0.057 tINS RF 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
17.503 0.000 tNET FF 2 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
17.560 0.057 tINS FF 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
17.560 0.000 tNET FF 2 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
17.617 0.057 tINS FF 1 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
17.617 0.000 tNET FF 2 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
17.674 0.057 tINS FF 1 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/COUT
17.674 0.000 tNET FF 2 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_5_0/CIN
18.237 0.563 tINS FF 1 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_5_0/SUM
18.237 0.000 tNET FF 1 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[5]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.579 12.579 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151 0.242 tNET RR 1 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[5]/CLK
13.121 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[5]
12.721 -0.400 tSu 1 R18C13[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[5]

Path Statistics:

Clock Skew -1.122
Setup Relationship 6.289
Logic Level 8
Arrival Clock Path Delay cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 4.363, 42.553%; route: 5.776, 56.326%; tC2Q: 0.115, 1.121%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack -5.460
Data Arrival Time 18.180
Data Required Time 12.721
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[4]
Launch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.289 6.289 active clock edge time
6.289 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
7.736 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
7.736 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.984 0.248 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.099 0.115 tNET RR 8 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
8.665 0.566 tINS RF 2 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[0]
12.402 3.737 tNET FF 2 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
13.360 0.958 tINS FF 1 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
13.360 0.000 tNET FF 2 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
13.417 0.057 tINS FF 1 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
13.417 0.000 tNET FF 2 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
13.474 0.057 tINS FF 1 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
13.474 0.000 tNET FF 2 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
13.531 0.057 tINS FF 1 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
13.531 0.000 tNET FF 2 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
13.588 0.057 tINS FF 1 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
13.588 0.000 tNET FF 2 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
13.645 0.057 tINS FF 1 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
13.645 0.000 tNET FF 2 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
13.702 0.057 tINS FF 1 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
13.702 0.000 tNET FF 2 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
13.759 0.057 tINS FF 1 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
14.327 0.568 tNET FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/I1
15.426 1.099 tINS FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/F
16.896 1.470 tNET FF 2 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/I1
17.446 0.550 tINS FR 1 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
17.446 0.000 tNET RR 2 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
17.503 0.057 tINS RF 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
17.503 0.000 tNET FF 2 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
17.560 0.057 tINS FF 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
17.560 0.000 tNET FF 2 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
17.617 0.057 tINS FF 1 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/COUT
17.617 0.000 tNET FF 2 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/CIN
18.180 0.563 tINS FF 1 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_4_0/SUM
18.180 0.000 tNET FF 1 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[4]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.579 12.579 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151 0.242 tNET RR 1 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[4]/CLK
13.121 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[4]
12.721 -0.400 tSu 1 R18C12[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[4]

Path Statistics:

Clock Skew -1.122
Setup Relationship 6.289
Logic Level 8
Arrival Clock Path Delay cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 4.306, 42.232%; route: 5.776, 56.641%; tC2Q: 0.115, 1.127%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack -5.403
Data Arrival Time 18.123
Data Required Time 12.721
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[3]
Launch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.289 6.289 active clock edge time
6.289 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
7.736 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
7.736 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.984 0.248 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.099 0.115 tNET RR 8 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
8.665 0.566 tINS RF 2 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[0]
12.402 3.737 tNET FF 2 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
13.360 0.958 tINS FF 1 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
13.360 0.000 tNET FF 2 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
13.417 0.057 tINS FF 1 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
13.417 0.000 tNET FF 2 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
13.474 0.057 tINS FF 1 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
13.474 0.000 tNET FF 2 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
13.531 0.057 tINS FF 1 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
13.531 0.000 tNET FF 2 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
13.588 0.057 tINS FF 1 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
13.588 0.000 tNET FF 2 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
13.645 0.057 tINS FF 1 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
13.645 0.000 tNET FF 2 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
13.702 0.057 tINS FF 1 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
13.702 0.000 tNET FF 2 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
13.759 0.057 tINS FF 1 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
14.327 0.568 tNET FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/I1
15.426 1.099 tINS FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/F
16.896 1.470 tNET FF 2 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/I1
17.446 0.550 tINS FR 1 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
17.446 0.000 tNET RR 2 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
17.503 0.057 tINS RF 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
17.503 0.000 tNET FF 2 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
17.560 0.057 tINS FF 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/COUT
17.560 0.000 tNET FF 2 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/CIN
18.123 0.563 tINS FF 1 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_3_0/SUM
18.123 0.000 tNET FF 1 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[3]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.579 12.579 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151 0.242 tNET RR 1 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[3]/CLK
13.121 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[3]
12.721 -0.400 tSu 1 R18C12[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[3]

Path Statistics:

Clock Skew -1.122
Setup Relationship 6.289
Logic Level 8
Arrival Clock Path Delay cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 4.249, 41.907%; route: 5.776, 56.960%; tC2Q: 0.115, 1.134%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack -5.346
Data Arrival Time 18.066
Data Required Time 12.721
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[2]
Launch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.289 6.289 active clock edge time
6.289 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
7.736 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
7.736 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.984 0.248 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.099 0.115 tNET RR 8 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
8.665 0.566 tINS RF 2 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[0]
12.402 3.737 tNET FF 2 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
13.360 0.958 tINS FF 1 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
13.360 0.000 tNET FF 2 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
13.417 0.057 tINS FF 1 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
13.417 0.000 tNET FF 2 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
13.474 0.057 tINS FF 1 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
13.474 0.000 tNET FF 2 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
13.531 0.057 tINS FF 1 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
13.531 0.000 tNET FF 2 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
13.588 0.057 tINS FF 1 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
13.588 0.000 tNET FF 2 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
13.645 0.057 tINS FF 1 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
13.645 0.000 tNET FF 2 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
13.702 0.057 tINS FF 1 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
13.702 0.000 tNET FF 2 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
13.759 0.057 tINS FF 1 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
14.327 0.568 tNET FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/I1
15.426 1.099 tINS FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/F
16.896 1.470 tNET FF 2 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/I1
17.446 0.550 tINS FR 1 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
17.446 0.000 tNET RR 2 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
17.503 0.057 tINS RF 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/COUT
17.503 0.000 tNET FF 2 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/CIN
18.066 0.563 tINS FF 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_2_0/SUM
18.066 0.000 tNET FF 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[2]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.579 12.579 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151 0.242 tNET RR 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[2]/CLK
13.121 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[2]
12.721 -0.400 tSu 1 R18C12[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[2]

Path Statistics:

Clock Skew -1.122
Setup Relationship 6.289
Logic Level 8
Arrival Clock Path Delay cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 4.192, 41.579%; route: 5.776, 57.282%; tC2Q: 0.115, 1.140%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack -5.289
Data Arrival Time 18.009
Data Required Time 12.721
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[1]
Launch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.289 6.289 active clock edge time
6.289 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
7.736 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
7.736 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.984 0.248 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.099 0.115 tNET RR 8 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
8.665 0.566 tINS RF 2 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[0]
12.402 3.737 tNET FF 2 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/I0
13.360 0.958 tINS FF 1 R18C5[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_1_0/COUT
13.360 0.000 tNET FF 2 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/CIN
13.417 0.057 tINS FF 1 R18C5[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_2_0/COUT
13.417 0.000 tNET FF 2 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/CIN
13.474 0.057 tINS FF 1 R18C5[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_3_0/COUT
13.474 0.000 tNET FF 2 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/CIN
13.531 0.057 tINS FF 1 R18C5[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_4_0/COUT
13.531 0.000 tNET FF 2 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/CIN
13.588 0.057 tINS FF 1 R18C5[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_5_0/COUT
13.588 0.000 tNET FF 2 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/CIN
13.645 0.057 tINS FF 1 R18C6[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_6_0/COUT
13.645 0.000 tNET FF 2 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/CIN
13.702 0.057 tINS FF 1 R18C6[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_7_0/COUT
13.702 0.000 tNET FF 2 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/CIN
13.759 0.057 tINS FF 1 R18C6[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_cry_8_0/COUT
14.327 0.568 tNET FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/I1
15.426 1.099 tINS FF 1 R18C6[3][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step8_cZ/F
16.896 1.470 tNET FF 2 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/I1
17.446 0.550 tINS FR 1 R18C12[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_0_0/COUT
17.446 0.000 tNET RR 2 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/CIN
18.009 0.563 tINS RF 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_3_cry_1_0/SUM
18.009 0.000 tNET FF 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.579 12.579 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151 0.242 tNET RR 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[1]/CLK
13.121 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[1]
12.721 -0.400 tSu 1 R18C12[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[1]

Path Statistics:

Clock Skew -1.122
Setup Relationship 6.289
Logic Level 8
Arrival Clock Path Delay cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 4.135, 41.246%; route: 5.776, 57.607%; tC2Q: 0.115, 1.146%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack -4.465
Data Arrival Time 193.286
Data Required Time 188.821
From syn_gen_inst/O_vs_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
188.552 188.552 active clock edge time
188.552 0.000 pix_clk
188.552 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
188.794 0.242 tNET RR 1 R18C30[0][A] syn_gen_inst/O_vs_s0/CLK
189.252 0.458 tC2Q RF 2 R18C30[0][A] syn_gen_inst/O_vs_s0/Q
190.394 1.142 tNET FF 1 R15C28[0][B] n173_s2/I0
191.020 0.626 tINS FF 4 R15C28[0][B] n173_s2/F
193.286 2.266 tNET FF 1 R11C24[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
188.679 188.679 active clock edge time
188.679 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
189.009 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
189.251 0.242 tNET RR 1 R11C24[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1/CLK
189.221 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1
188.821 -0.400 tSu 1 R11C24[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1

Path Statistics:

Clock Skew 0.330
Setup Relationship 0.127
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 0.626, 13.935%; route: 3.408, 75.863%; tC2Q: 0.458, 10.203%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack -3.646
Data Arrival Time 192.467
Data Required Time 188.821
From syn_gen_inst/O_vs_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
188.552 188.552 active clock edge time
188.552 0.000 pix_clk
188.552 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
188.794 0.242 tNET RR 1 R18C30[0][A] syn_gen_inst/O_vs_s0/CLK
189.252 0.458 tC2Q RF 2 R18C30[0][A] syn_gen_inst/O_vs_s0/Q
190.394 1.142 tNET FF 1 R15C28[0][B] n173_s2/I0
191.020 0.626 tINS FF 4 R15C28[0][B] n173_s2/F
192.467 1.447 tNET FF 1 R15C25[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
188.679 188.679 active clock edge time
188.679 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
189.009 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
189.251 0.242 tNET RR 1 R15C25[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0/CLK
189.221 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0
188.821 -0.400 tSu 1 R15C25[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0

Path Statistics:

Clock Skew 0.330
Setup Relationship 0.127
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 0.626, 17.043%; route: 2.589, 70.478%; tC2Q: 0.458, 12.478%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack -3.054
Data Arrival Time 1223.322
Data Required Time 1220.267
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_10_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_10_s0
Launch Clk ch0_vfb_clk_in:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.000 1220.000 active clock edge time
1220.000 0.000 ch0_vfb_clk_in
1220.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1220.946 0.946 tNET RR 1 R5C22[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_10_s0/CLK
1221.404 0.458 tC2Q RF 2 R5C22[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_10_s0/Q
1223.322 1.918 tNET FF 1 R8C23[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.125 1220.125 active clock edge time
1220.125 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1220.455 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1220.697 0.242 tNET RR 1 R8C23[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_10_s0/CLK
1220.667 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_10_s0
1220.267 -0.400 tSu 1 R8C23[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_10_s0

Path Statistics:

Clock Skew -0.374
Setup Relationship 0.125
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.946, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.918, 80.709%; tC2Q: 0.458, 19.291%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack -3.005
Data Arrival Time 1147.597
Data Required Time 1144.592
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_8_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_8_s0
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1144.653 1144.653 active clock edge time
1144.653 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1144.983 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1145.225 0.242 tNET RR 1 R5C27[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_8_s0/CLK
1145.683 0.458 tC2Q RF 1 R5C27[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wptr_8_s0/Q
1147.597 1.914 tNET FF 1 R8C28[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1144.780 1144.780 active clock edge time
1144.780 0.000 pix_clk
1144.780 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
1145.022 0.242 tNET RR 1 R8C28[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_8_s0/CLK
1144.992 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_8_s0
1144.592 -0.400 tSu 1 R8C28[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rq1_wptr_8_s0

Path Statistics:

Clock Skew -0.330
Setup Relationship 0.127
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.914, 80.676%; tC2Q: 0.458, 19.324%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack -2.833
Data Arrival Time 191.655
Data Required Time 188.821
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_10_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_10_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
188.552 188.552 active clock edge time
188.552 0.000 pix_clk
188.552 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
188.794 0.242 tNET RR 1 R11C30[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_10_s0/CLK
189.252 0.458 tC2Q RF 2 R11C30[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_10_s0/Q
191.655 2.402 tNET FF 1 R8C27[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
188.679 188.679 active clock edge time
188.679 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
189.009 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
189.251 0.242 tNET RR 1 R8C27[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_10_s0/CLK
189.221 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_10_s0
188.821 -0.400 tSu 1 R8C27[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_10_s0

Path Statistics:

Clock Skew 0.330
Setup Relationship 0.127
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.402, 83.977%; tC2Q: 0.458, 16.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack -2.829
Data Arrival Time 191.650
Data Required Time 188.821
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_4_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_4_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
188.552 188.552 active clock edge time
188.552 0.000 pix_clk
188.552 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
188.794 0.242 tNET RR 1 R8C26[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_4_s0/CLK
189.252 0.458 tC2Q RF 1 R8C26[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_4_s0/Q
191.650 2.398 tNET FF 1 R8C26[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
188.679 188.679 active clock edge time
188.679 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
189.009 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
189.251 0.242 tNET RR 1 R8C26[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_4_s0/CLK
189.221 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_4_s0
188.821 -0.400 tSu 1 R8C26[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_4_s0

Path Statistics:

Clock Skew 0.330
Setup Relationship 0.127
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 2.398, 83.954%; tC2Q: 0.458, 16.046%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack -2.736
Data Arrival Time 1223.003
Data Required Time 1220.267
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_1_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_1_s0
Launch Clk ch0_vfb_clk_in:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.000 1220.000 active clock edge time
1220.000 0.000 ch0_vfb_clk_in
1220.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1220.946 0.946 tNET RR 1 R4C19[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_1_s0/CLK
1221.404 0.458 tC2Q RF 1 R4C19[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_1_s0/Q
1223.003 1.599 tNET FF 1 R8C19[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.125 1220.125 active clock edge time
1220.125 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1220.455 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1220.697 0.242 tNET RR 1 R8C19[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_1_s0/CLK
1220.667 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_1_s0
1220.267 -0.400 tSu 1 R8C19[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_1_s0

Path Statistics:

Clock Skew -0.374
Setup Relationship 0.125
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.946, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.599, 77.724%; tC2Q: 0.458, 22.276%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack -2.592
Data Arrival Time 15.312
Data Required Time 12.721
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[0]
Launch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.289 6.289 active clock edge time
6.289 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
7.736 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
7.736 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
7.984 0.248 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.099 0.115 tNET RR 8 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
8.665 0.566 tINS RF 2 DLL_BL HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[2]
12.402 3.737 tNET FF 2 R18C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_3_0/I0
13.360 0.958 tINS FF 1 R18C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_3_0/COUT
13.360 0.000 tNET FF 2 R18C7[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_4_0/CIN
13.417 0.057 tINS FF 1 R18C7[2][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_4_0/COUT
13.417 0.000 tNET FF 2 R18C7[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_5_0/CIN
13.474 0.057 tINS FF 1 R18C7[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_5_0/COUT
13.474 0.000 tNET FF 2 R18C8[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_6_0/CIN
13.531 0.057 tINS FF 1 R18C8[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_6_0/COUT
13.531 0.000 tNET FF 2 R18C8[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_7_0/CIN
13.588 0.057 tINS FF 1 R18C8[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_7_0/COUT
13.588 0.000 tNET FF 2 R18C8[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_8_0/CIN
13.645 0.057 tINS FF 1 R18C8[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/un1_step_1_cry_8_0/COUT
14.213 0.568 tNET FF 1 R18C8[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_1_3/I2
15.312 1.099 tINS FF 1 R18C8[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_1_3/F
15.312 0.000 tNET FF 1 R18C8[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[0]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
12.579 12.579 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151 0.242 tNET RR 1 R18C8[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[0]/CLK
13.121 -0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[0]
12.721 -0.400 tSu 1 R18C8[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_Z[0]

Path Statistics:

Clock Skew -1.122
Setup Relationship 6.289
Logic Level 5
Arrival Clock Path Delay cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay cell: 2.908, 39.683%; route: 4.306, 58.749%; tC2Q: 0.115, 1.568%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack -2.566
Data Arrival Time 1222.833
Data Required Time 1220.267
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_0_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0
Launch Clk ch0_vfb_clk_in:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.000 1220.000 active clock edge time
1220.000 0.000 ch0_vfb_clk_in
1220.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1220.946 0.946 tNET RR 1 R7C19[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_0_s0/CLK
1221.404 0.458 tC2Q RF 1 R7C19[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_0_s0/Q
1222.833 1.429 tNET FF 1 R6C21[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.125 1220.125 active clock edge time
1220.125 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1220.455 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1220.697 0.242 tNET RR 1 R6C21[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0/CLK
1220.667 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0
1220.267 -0.400 tSu 1 R6C21[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0

Path Statistics:

Clock Skew -0.374
Setup Relationship 0.125
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.946, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.429, 75.715%; tC2Q: 0.458, 24.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack -2.566
Data Arrival Time 1222.833
Data Required Time 1220.267
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_2_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_2_s0
Launch Clk ch0_vfb_clk_in:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.000 1220.000 active clock edge time
1220.000 0.000 ch0_vfb_clk_in
1220.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1220.946 0.946 tNET RR 1 R3C20[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_2_s0/CLK
1221.404 0.458 tC2Q RF 1 R3C20[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_2_s0/Q
1222.833 1.429 tNET FF 1 R2C19[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.125 1220.125 active clock edge time
1220.125 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1220.455 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1220.697 0.242 tNET RR 1 R2C19[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_2_s0/CLK
1220.667 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_2_s0
1220.267 -0.400 tSu 1 R2C19[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_2_s0

Path Statistics:

Clock Skew -0.374
Setup Relationship 0.125
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.946, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.429, 75.715%; tC2Q: 0.458, 24.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack -2.566
Data Arrival Time 1222.833
Data Required Time 1220.267
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_3_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_3_s0
Launch Clk ch0_vfb_clk_in:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.000 1220.000 active clock edge time
1220.000 0.000 ch0_vfb_clk_in
1220.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1220.946 0.946 tNET RR 1 R6C19[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_3_s0/CLK
1221.404 0.458 tC2Q RF 1 R6C19[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wptr_3_s0/Q
1222.833 1.429 tNET FF 1 R7C18[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1220.125 1220.125 active clock edge time
1220.125 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1220.455 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1220.697 0.242 tNET RR 1 R7C18[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_3_s0/CLK
1220.667 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_3_s0
1220.267 -0.400 tSu 1 R7C18[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_3_s0

Path Statistics:

Clock Skew -0.374
Setup Relationship 0.125
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.946, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.429, 75.715%; tC2Q: 0.458, 24.285%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -0.334
Data Arrival Time 1.440
Data Required Time 1.774
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CLK
0.846 0.333 tC2Q RR 13 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q
1.440 0.593 tNET RR 1 IOB7[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB7[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/FCLK
1.774 0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4
1.774 0.000 tHld 1 IOB7[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.593, 64.027%; tC2Q: 0.333, 35.973%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path2

Path Summary:

Slack -0.334
Data Arrival Time 1.440
Data Required Time 1.774
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CLK
0.846 0.333 tC2Q RR 13 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q
1.440 0.593 tNET RR 1 IOB7[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB7[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4/FCLK
1.774 0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4
1.774 0.000 tHld 1 IOB7[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.593, 64.027%; tC2Q: 0.333, 35.973%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path3

Path Summary:

Slack 0.156
Data Arrival Time 1.929
Data Required Time 1.774
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CLK
0.846 0.333 tC2Q RR 13 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q
1.929 1.083 tNET RR 1 IOB14[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB14[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/FCLK
1.774 0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
1.774 0.000 tHld 1 IOB14[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.083, 76.462%; tC2Q: 0.333, 23.538%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path4

Path Summary:

Slack 0.156
Data Arrival Time 1.929
Data Required Time 1.774
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CLK
0.846 0.333 tC2Q RR 13 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q
1.929 1.083 tNET RR 1 IOB14[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB14[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/FCLK
1.774 0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
1.774 0.000 tHld 1 IOB14[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.083, 76.462%; tC2Q: 0.333, 23.538%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path5

Path Summary:

Slack 0.432
Data Arrival Time 2.206
Data Required Time 1.774
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CLK
0.846 0.333 tC2Q RR 13 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q
2.206 1.359 tNET RR 1 IOB24[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB24[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/FCLK
1.774 0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
1.774 0.000 tHld 1 IOB24[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.359, 80.308%; tC2Q: 0.333, 19.692%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path6

Path Summary:

Slack 0.438
Data Arrival Time 2.212
Data Required Time 1.774
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CLK
0.846 0.333 tC2Q RR 13 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q
2.212 1.366 tNET RR 1 IOB25[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB25[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/FCLK
1.774 0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
1.774 0.000 tHld 1 IOB25[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.366, 80.380%; tC2Q: 0.333, 19.620%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path7

Path Summary:

Slack 0.438
Data Arrival Time 2.212
Data Required Time 1.774
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CLK
0.846 0.333 tC2Q RR 13 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q
2.212 1.366 tNET RR 1 IOB25[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB25[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/FCLK
1.774 0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
1.774 0.000 tHld 1 IOB25[B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.366, 80.380%; tC2Q: 0.333, 19.620%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path8

Path Summary:

Slack 0.480
Data Arrival Time 2.253
Data Required Time 1.774
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CLK
0.846 0.333 tC2Q RR 13 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/Q
2.253 1.407 tNET RR 1 IOB29[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
1.446 1.446 tCL RR 1 PLL_L GW_PLLVR_inst/pllvr_inst/CLKOUT
1.446 0.000 tNET RR 3 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
1.659 0.213 tINS RR 22 - HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
1.744 0.085 tNET RR 1 IOB29[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/FCLK
1.774 0.030 tUnc HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
1.774 0.000 tHld 1 IOB29[A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew 1.230
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 1.407, 80.847%; tC2Q: 0.333, 19.153%
Required Clock Path Delay cell: 0.213, 71.550%; route: 0.085, 28.450%

Path9

Path Summary:

Slack 0.556
Data Arrival Time 1.084
Data Required Time 0.528
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state_Z[10]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep1
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R11C10[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state_Z[10]/CLK
0.846 0.333 tC2Q RR 4 R11C10[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state_Z[10]/Q
1.084 0.238 tNET RR 1 R11C10[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R11C10[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep1/CLK
0.528 0.015 tHld 1 R11C10[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path10

Path Summary:

Slack 0.556
Data Arrival Time 1.084
Data Required Time 0.528
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state_Z[10]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep2
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R11C10[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state_Z[10]/CLK
0.846 0.333 tC2Q RR 4 R11C10[1][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state_Z[10]/Q
1.084 0.238 tNET RR 1 R11C10[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep2/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R11C10[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep2/CLK
0.528 0.015 tHld 1 R11C10[0][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_rep2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path11

Path Summary:

Slack 0.562
Data Arrival Time 1.090
Data Required Time 0.528
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib_done[0]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]
Launch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib_done[0]/CLK
0.846 0.333 tC2Q RR 3 R12C7[2][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib_done[0]/Q
1.090 0.244 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]/CLK
0.528 0.015 tHld 1 R12C7[1][B] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].calib[0]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.244, 42.242%; tC2Q: 0.333, 57.758%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path12

Path Summary:

Slack 0.576
Data Arrival Time 1.120
Data Required Time 0.543
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_0_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_0_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pix_clk
0.000 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
0.183 0.183 tNET RR 1 R7C26[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_0_s0/CLK
0.516 0.333 tC2Q RF 1 R7C26[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_0_s0/Q
1.120 0.603 tNET FF 1 R7C26[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R7C26[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_0_s0/CLK
0.543 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_0_s0
0.543 0.000 tHld 1 R7C26[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_0_s0

Path Statistics:

Clock Skew 0.330
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path13

Path Summary:

Slack 0.576
Data Arrival Time 1.120
Data Required Time 0.543
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_2_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_2_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pix_clk
0.000 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
0.183 0.183 tNET RR 1 R7C25[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_2_s0/CLK
0.516 0.333 tC2Q RF 1 R7C25[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_2_s0/Q
1.120 0.603 tNET FF 1 R7C24[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R7C24[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_2_s0/CLK
0.543 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_2_s0
0.543 0.000 tHld 1 R7C24[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_2_s0

Path Statistics:

Clock Skew 0.330
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path14

Path Summary:

Slack 0.576
Data Arrival Time 1.120
Data Required Time 0.543
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_5_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_5_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pix_clk
0.000 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
0.183 0.183 tNET RR 1 R8C25[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_5_s0/CLK
0.516 0.333 tC2Q RF 1 R8C25[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_5_s0/Q
1.120 0.603 tNET FF 1 R8C25[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R8C25[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_5_s0/CLK
0.543 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_5_s0
0.543 0.000 tHld 1 R8C25[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_5_s0

Path Statistics:

Clock Skew 0.330
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path15

Path Summary:

Slack 0.576
Data Arrival Time 1.120
Data Required Time 0.543
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_6_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_6_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pix_clk
0.000 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
0.183 0.183 tNET RR 1 R7C25[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_6_s0/CLK
0.516 0.333 tC2Q RF 1 R7C25[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_6_s0/Q
1.120 0.603 tNET FF 1 R7C25[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R7C25[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_6_s0/CLK
0.543 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_6_s0
0.543 0.000 tHld 1 R7C25[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_6_s0

Path Statistics:

Clock Skew 0.330
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path16

Path Summary:

Slack 0.576
Data Arrival Time 1.120
Data Required Time 0.543
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_8_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_8_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pix_clk
0.000 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
0.183 0.183 tNET RR 1 R8C28[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_8_s0/CLK
0.516 0.333 tC2Q RF 1 R8C28[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_8_s0/Q
1.120 0.603 tNET FF 1 R8C27[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R8C27[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_8_s0/CLK
0.543 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_8_s0
0.543 0.000 tHld 1 R8C27[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_8_s0

Path Statistics:

Clock Skew 0.330
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path17

Path Summary:

Slack 0.595
Data Arrival Time 1.138
Data Required Time 0.543
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_1_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_1_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pix_clk
0.000 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
0.183 0.183 tNET RR 1 R8C25[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_1_s0/CLK
0.516 0.333 tC2Q RR 1 R8C25[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_1_s0/Q
1.138 0.621 tNET RR 1 R8C25[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R8C25[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_1_s0/CLK
0.543 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_1_s0
0.543 0.000 tHld 1 R8C25[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_1_s0

Path Statistics:

Clock Skew 0.330
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.621, 65.086%; tC2Q: 0.333, 34.914%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path18

Path Summary:

Slack 0.595
Data Arrival Time 1.138
Data Required Time 0.543
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_3_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_3_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pix_clk
0.000 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
0.183 0.183 tNET RR 1 R8C26[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_3_s0/CLK
0.516 0.333 tC2Q RR 1 R8C26[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_3_s0/Q
1.138 0.621 tNET RR 1 R8C26[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R8C26[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_3_s0/CLK
0.543 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_3_s0
0.543 0.000 tHld 1 R8C26[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_3_s0

Path Statistics:

Clock Skew 0.330
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.621, 65.086%; tC2Q: 0.333, 34.914%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path19

Path Summary:

Slack 0.595
Data Arrival Time 1.138
Data Required Time 0.543
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_7_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_7_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pix_clk
0.000 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
0.183 0.183 tNET RR 1 R7C26[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_7_s0/CLK
0.516 0.333 tC2Q RR 1 R7C26[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_7_s0/Q
1.138 0.621 tNET RR 1 R7C26[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R7C26[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_7_s0/CLK
0.543 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_7_s0
0.543 0.000 tHld 1 R7C26[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_7_s0

Path Statistics:

Clock Skew 0.330
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.621, 65.086%; tC2Q: 0.333, 34.914%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path20

Path Summary:

Slack 0.595
Data Arrival Time 1.138
Data Required Time 0.543
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_9_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_9_s0
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 pix_clk
0.000 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
0.183 0.183 tNET RR 1 R7C25[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_9_s0/CLK
0.516 0.333 tC2Q RR 1 R7C25[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rptr_9_s0/Q
1.138 0.621 tNET RR 1 R7C25[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330 0.330 tCL RR 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513 0.183 tNET RR 1 R7C25[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_9_s0/CLK
0.543 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_9_s0
0.543 0.000 tHld 1 R7C25[1][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq1_rptr_9_s0

Path Statistics:

Clock Skew 0.330
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.621, 65.086%; tC2Q: 0.333, 34.914%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%

Path21

Path Summary:

Slack 0.708
Data Arrival Time 3.444
Data Required Time 2.737
From u_OV2640_Controller/I2C/divider_0_s2
To u_OV2640_Controller/I2C/divider_0_s2
Launch Clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk
2.552 2.552 tCL RR 84 PLL_R TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
2.737 0.185 tNET RR 1 R14C5[0][A] u_OV2640_Controller/I2C/divider_0_s2/CLK
3.070 0.333 tC2Q RR 6 R14C5[0][A] u_OV2640_Controller/I2C/divider_0_s2/Q
3.072 0.002 tNET RR 1 R14C5[0][A] u_OV2640_Controller/I2C/n369_s1/I0
3.444 0.372 tINS RF 1 R14C5[0][A] u_OV2640_Controller/I2C/n369_s1/F
3.444 0.000 tNET FF 1 R14C5[0][A] u_OV2640_Controller/I2C/divider_0_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk
2.552 2.552 tCL RR 84 PLL_R TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
2.737 0.185 tNET RR 1 R14C5[0][A] u_OV2640_Controller/I2C/divider_0_s2/CLK
2.737 0.000 tHld 1 R14C5[0][A] u_OV2640_Controller/I2C/divider_0_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path22

Path Summary:

Slack 0.708
Data Arrival Time 3.444
Data Required Time 2.737
From u_OV2640_Controller/I2C/divider_3_s1
To u_OV2640_Controller/I2C/divider_3_s1
Launch Clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk
2.552 2.552 tCL RR 84 PLL_R TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
2.737 0.185 tNET RR 1 R9C5[1][A] u_OV2640_Controller/I2C/divider_3_s1/CLK
3.070 0.333 tC2Q RR 3 R9C5[1][A] u_OV2640_Controller/I2C/divider_3_s1/Q
3.072 0.002 tNET RR 1 R9C5[1][A] u_OV2640_Controller/I2C/n366_s1/I2
3.444 0.372 tINS RF 1 R9C5[1][A] u_OV2640_Controller/I2C/n366_s1/F
3.444 0.000 tNET FF 1 R9C5[1][A] u_OV2640_Controller/I2C/divider_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk
2.552 2.552 tCL RR 84 PLL_R TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
2.737 0.185 tNET RR 1 R9C5[1][A] u_OV2640_Controller/I2C/divider_3_s1/CLK
2.737 0.000 tHld 1 R9C5[1][A] u_OV2640_Controller/I2C/divider_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path23

Path Summary:

Slack 0.708
Data Arrival Time 3.444
Data Required Time 2.737
From u_OV2640_Controller/I2C/divider_5_s1
To u_OV2640_Controller/I2C/divider_5_s1
Launch Clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk
2.552 2.552 tCL RR 84 PLL_R TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
2.737 0.185 tNET RR 1 R9C5[0][A] u_OV2640_Controller/I2C/divider_5_s1/CLK
3.070 0.333 tC2Q RR 3 R9C5[0][A] u_OV2640_Controller/I2C/divider_5_s1/Q
3.072 0.002 tNET RR 1 R9C5[0][A] u_OV2640_Controller/I2C/n364_s1/I2
3.444 0.372 tINS RF 1 R9C5[0][A] u_OV2640_Controller/I2C/n364_s1/F
3.444 0.000 tNET FF 1 R9C5[0][A] u_OV2640_Controller/I2C/divider_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk
2.552 2.552 tCL RR 84 PLL_R TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
2.737 0.185 tNET RR 1 R9C5[0][A] u_OV2640_Controller/I2C/divider_5_s1/CLK
2.737 0.000 tHld 1 R9C5[0][A] u_OV2640_Controller/I2C/divider_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path24

Path Summary:

Slack 0.708
Data Arrival Time 3.444
Data Required Time 2.737
From u_OV2640_Controller/I2C/divider_6_s1
To u_OV2640_Controller/I2C/divider_6_s1
Launch Clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk
2.552 2.552 tCL RR 84 PLL_R TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
2.737 0.185 tNET RR 1 R9C3[0][A] u_OV2640_Controller/I2C/divider_6_s1/CLK
3.070 0.333 tC2Q RR 6 R9C3[0][A] u_OV2640_Controller/I2C/divider_6_s1/Q
3.072 0.002 tNET RR 1 R9C3[0][A] u_OV2640_Controller/I2C/n363_s1/I0
3.444 0.372 tINS RF 1 R9C3[0][A] u_OV2640_Controller/I2C/n363_s1/F
3.444 0.000 tNET FF 1 R9C3[0][A] u_OV2640_Controller/I2C/divider_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk
2.552 2.552 tCL RR 84 PLL_R TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
2.737 0.185 tNET RR 1 R9C3[0][A] u_OV2640_Controller/I2C/divider_6_s1/CLK
2.737 0.000 tHld 1 R9C3[0][A] u_OV2640_Controller/I2C/divider_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path25

Path Summary:

Slack 0.708
Data Arrival Time 2.518
Data Required Time 1.811
From HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_fast_Z[1]
To HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_fast_Z[1]
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C9[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_fast_Z[1]/CLK
2.144 0.333 tC2Q RR 3 R3C9[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_fast_Z[1]/Q
2.146 0.002 tNET RR 1 R3C9[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/N_76_i_fast_cZ/I2
2.518 0.372 tINS RF 1 R3C9[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/N_76_i_fast_cZ/F
2.518 0.000 tNET FF 1 R3C9[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_fast_Z[1]/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C9[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_fast_Z[1]/CLK
1.811 0.000 tHld 1 R3C9[0][A] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_fast_Z[1]

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack -5.792
Data Arrival Time 46.363
Data Required Time 40.571
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 IOR17[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 IOR17[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk/PCLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk
40.571 -0.045 tSu 1 IOR17[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path2

Path Summary:

Slack -5.792
Data Arrival Time 46.363
Data Required Time 40.571
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 IOR15[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 IOR15[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/PCLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b
40.571 -0.045 tSu 1 IOR15[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack -5.792
Data Arrival Time 46.363
Data Required Time 40.571
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 IOR11[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 IOR11[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g/PCLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g
40.571 -0.045 tSu 1 IOR11[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack -5.792
Data Arrival Time 46.363
Data Required Time 40.571
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 IOR2[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 IOR2[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r/PCLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r
40.571 -0.045 tSu 1 IOR2[A] DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R17C36[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R17C36[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0
40.573 -0.043 tSu 1 R17C36[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R13C33[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R13C33[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0
40.573 -0.043 tSu 1 R13C33[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R15C36[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R15C36[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0
40.573 -0.043 tSu 1 R15C36[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R14C34[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R14C34[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0
40.573 -0.043 tSu 1 R14C34[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R15C34[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R15C34[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0
40.573 -0.043 tSu 1 R15C34[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R14C35[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R14C35[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0
40.573 -0.043 tSu 1 R14C35[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R14C34[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R14C34[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0
40.573 -0.043 tSu 1 R14C34[1][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R14C35[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R14C35[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0
40.573 -0.043 tSu 1 R14C35[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R14C35[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R14C35[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0
40.573 -0.043 tSu 1 R14C35[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R13C35[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R13C35[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0
40.573 -0.043 tSu 1 R13C35[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R15C36[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R15C36[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0
40.573 -0.043 tSu 1 R15C36[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R15C34[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R15C34[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0
40.573 -0.043 tSu 1 R15C34[0][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R13C32[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R13C32[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0
40.573 -0.043 tSu 1 R13C32[2][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R15C31[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R15C31[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0
40.573 -0.043 tSu 1 R15C31[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R15C31[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R15C31[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0
40.573 -0.043 tSu 1 R15C31[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R13C32[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R13C32[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
40.573 -0.043 tSu 1 R13C32[2][B] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R14C33[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R14C33[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0
40.573 -0.043 tSu 1 R14C33[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R15C34[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R15C34[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0
40.573 -0.043 tSu 1 R15C34[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R13C34[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R13C34[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0
40.573 -0.043 tSu 1 R13C34[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R13C33[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R13C33[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0
40.573 -0.043 tSu 1 R13C33[1][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack -5.790
Data Arrival Time 46.363
Data Required Time 40.573
From u_Reset_Sync/reset_cnt_3_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0
Launch Clk I_clk:[R]
Latch Clk pix_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
38.019 0.982 tINS RR 97 IOT13[A] I_clk_ibuf/O
39.380 1.361 tNET RR 1 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/CLK
39.838 0.458 tC2Q RR 2 R11C30[1][B] u_Reset_Sync/reset_cnt_3_s0/Q
40.261 0.422 tNET RR 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I3
41.360 1.099 tINS RF 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
42.852 1.492 tNET FF 1 R3C30[3][A] hdmi_rst_n_s0/I1
43.884 1.032 tINS FF 119 R3C30[3][A] hdmi_rst_n_s0/F
46.363 2.479 tNET FF 1 R13C34[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
40.404 40.404 active clock edge time
40.404 0.000 pix_clk
40.404 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
40.646 0.242 tNET RR 1 R13C34[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0/CLK
40.616 -0.030 tUnc DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0
40.573 -0.043 tSu 1 R13C34[0][A] DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0

Path Statistics:

Clock Skew -2.101
Setup Relationship 3.367
Logic Level 3
Arrival Clock Path Delay cell: 0.982, 41.904%; route: 1.361, 58.096%
Arrival Data Path Delay cell: 2.131, 30.519%; route: 4.393, 62.917%; tC2Q: 0.458, 6.564%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.242, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.869
Data Arrival Time 1240.428
Data Required Time 1239.559
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s1
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1239.056 1239.056 active clock edge time
1239.056 0.000 pix_clk
1239.056 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
1239.239 0.183 tNET RR 1 R14C26[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/CLK
1239.572 0.333 tC2Q RR 5 R14C26[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/Q
1240.428 0.856 tNET RR 1 R8C26[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1238.992 1238.992 active clock edge time
1238.992 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1239.323 0.330 tCL FF 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1239.514 0.191 tNET FF 1 R8C26[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s1/CLK
1239.544 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s1
1239.559 0.015 tHld 1 R8C26[2][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s1

Path Statistics:

Clock Skew 0.338
Hold Relationship -0.064
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 71.963%; tC2Q: 0.333, 28.037%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.191, 100.000%

Path2

Path Summary:

Slack 0.869
Data Arrival Time 1240.428
Data Required Time 1239.559
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s1
Launch Clk pix_clk:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1239.056 1239.056 active clock edge time
1239.056 0.000 pix_clk
1239.056 0.000 tCL RR 220 RIGHTSIDE[1] u_clkdiv/CLKOUT
1239.239 0.183 tNET RR 1 R14C26[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/CLK
1239.572 0.333 tC2Q RR 5 R14C26[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/Q
1240.428 0.856 tNET RR 1 R8C26[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1238.992 1238.992 active clock edge time
1238.992 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1239.323 0.330 tCL FF 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1239.514 0.191 tNET FF 1 R8C26[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s1/CLK
1239.544 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s1
1239.559 0.015 tHld 1 R8C26[2][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s1

Path Statistics:

Clock Skew 0.338
Hold Relationship -0.064
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.856, 71.963%; tC2Q: 0.333, 28.037%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.191, 100.000%

Path3

Path Summary:

Slack 1.001
Data Arrival Time 1001.567
Data Required Time 1000.566
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1
Launch Clk ch0_vfb_clk_in:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1000.000 1000.000 active clock edge time
1000.000 0.000 ch0_vfb_clk_in
1000.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1000.684 0.684 tNET RR 1 R15C18[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/CLK
1001.017 0.333 tC2Q RR 6 R15C18[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/Q
1001.567 0.550 tNET RR 1 R11C17[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
999.999 999.999 active clock edge time
999.999 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1000.329 0.330 tCL FF 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1000.520 0.191 tNET FF 1 R11C17[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1/CLK
1000.550 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1
1000.565 0.015 tHld 1 R11C17[0][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s1

Path Statistics:

Clock Skew -0.162
Hold Relationship -0.001
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.550, 62.269%; tC2Q: 0.333, 37.731%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.191, 100.000%

Path4

Path Summary:

Slack 1.001
Data Arrival Time 1001.567
Data Required Time 1000.566
From Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s1
Launch Clk ch0_vfb_clk_in:[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
1000.000 1000.000 active clock edge time
1000.000 0.000 ch0_vfb_clk_in
1000.000 0.000 tCL RR 120 R2C19[3][A] ch0_vfb_clk_in_s0/F
1000.684 0.684 tNET RR 1 R15C18[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/CLK
1001.017 0.333 tC2Q RR 6 R15C18[1][A] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/Q
1001.567 0.550 tNET RR 1 R11C17[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s1/PRESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
999.999 999.999 active clock edge time
999.999 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1000.329 0.330 tCL FF 629 BOTTOMSIDE[1] HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1000.520 0.191 tNET FF 1 R11C17[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s1/CLK
1000.550 0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s1
1000.565 0.015 tHld 1 R11C17[0][B] Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s1

Path Statistics:

Clock Skew -0.162
Hold Relationship -0.001
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.684, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.550, 62.269%; tC2Q: 0.333, 37.731%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.191, 100.000%

Path5

Path Summary:

Slack 1.892
Data Arrival Time 3.718
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_22_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.718 0.954 tNET RR 1 R4C30[1][B] run_cnt_22_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C30[1][B] run_cnt_22_s0/CLK
1.826 0.015 tHld 1 R4C30[1][B] run_cnt_22_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.188%; route: 1.189, 62.333%; tC2Q: 0.333, 17.479%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path6

Path Summary:

Slack 1.892
Data Arrival Time 3.718
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_23_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.718 0.954 tNET RR 1 R4C30[1][A] run_cnt_23_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C30[1][A] run_cnt_23_s0/CLK
1.826 0.015 tHld 1 R4C30[1][A] run_cnt_23_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.188%; route: 1.189, 62.333%; tC2Q: 0.333, 17.479%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path7

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_0_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R3C30[1][A] run_cnt_0_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C30[1][A] run_cnt_0_s0/CLK
1.826 0.015 tHld 1 R3C30[1][A] run_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path8

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_1_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R3C31[1][B] run_cnt_1_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C31[1][B] run_cnt_1_s0/CLK
1.826 0.015 tHld 1 R3C31[1][B] run_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path9

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_2_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R3C31[0][A] run_cnt_2_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C31[0][A] run_cnt_2_s0/CLK
1.826 0.015 tHld 1 R3C31[0][A] run_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path10

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_6_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R3C31[0][B] run_cnt_6_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C31[0][B] run_cnt_6_s0/CLK
1.826 0.015 tHld 1 R3C31[0][B] run_cnt_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path11

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_9_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R4C31[1][A] run_cnt_9_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C31[1][A] run_cnt_9_s0/CLK
1.826 0.015 tHld 1 R4C31[1][A] run_cnt_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path12

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_10_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R4C32[0][A] run_cnt_10_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C32[0][A] run_cnt_10_s0/CLK
1.826 0.015 tHld 1 R4C32[0][A] run_cnt_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path13

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_11_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R4C32[1][B] run_cnt_11_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C32[1][B] run_cnt_11_s0/CLK
1.826 0.015 tHld 1 R4C32[1][B] run_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path14

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_12_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R4C32[1][A] run_cnt_12_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C32[1][A] run_cnt_12_s0/CLK
1.826 0.015 tHld 1 R4C32[1][A] run_cnt_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path15

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_13_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R4C31[0][B] run_cnt_13_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C31[0][B] run_cnt_13_s0/CLK
1.826 0.015 tHld 1 R4C31[0][B] run_cnt_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path16

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_14_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R3C30[2][A] run_cnt_14_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C30[2][A] run_cnt_14_s0/CLK
1.826 0.015 tHld 1 R3C30[2][A] run_cnt_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path17

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_15_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R3C30[1][B] run_cnt_15_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C30[1][B] run_cnt_15_s0/CLK
1.826 0.015 tHld 1 R3C30[1][B] run_cnt_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path18

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_16_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R4C32[0][B] run_cnt_16_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C32[0][B] run_cnt_16_s0/CLK
1.826 0.015 tHld 1 R4C32[0][B] run_cnt_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path19

Path Summary:

Slack 1.898
Data Arrival Time 3.724
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_19_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.724 0.960 tNET RR 1 R3C31[1][A] run_cnt_19_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C31[1][A] run_cnt_19_s0/CLK
1.826 0.015 tHld 1 R3C31[1][A] run_cnt_19_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.123%; route: 1.195, 62.455%; tC2Q: 0.333, 17.422%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path20

Path Summary:

Slack 1.904
Data Arrival Time 3.730
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_3_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.730 0.967 tNET RR 1 R3C32[0][B] run_cnt_3_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C32[0][B] run_cnt_3_s0/CLK
1.826 0.015 tHld 1 R3C32[0][B] run_cnt_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.057%; route: 1.201, 62.577%; tC2Q: 0.333, 17.366%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path21

Path Summary:

Slack 1.904
Data Arrival Time 3.730
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_17_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.730 0.967 tNET RR 1 R3C32[1][B] run_cnt_17_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C32[1][B] run_cnt_17_s0/CLK
1.826 0.015 tHld 1 R3C32[1][B] run_cnt_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.057%; route: 1.201, 62.577%; tC2Q: 0.333, 17.366%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path22

Path Summary:

Slack 1.904
Data Arrival Time 3.730
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_18_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.730 0.967 tNET RR 1 R3C32[2][A] run_cnt_18_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C32[2][A] run_cnt_18_s0/CLK
1.826 0.015 tHld 1 R3C32[2][A] run_cnt_18_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.057%; route: 1.201, 62.577%; tC2Q: 0.333, 17.366%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path23

Path Summary:

Slack 1.904
Data Arrival Time 3.730
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_21_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.730 0.967 tNET RR 1 R3C32[1][A] run_cnt_21_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R3C32[1][A] run_cnt_21_s0/CLK
1.826 0.015 tHld 1 R3C32[1][A] run_cnt_21_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 20.057%; route: 1.201, 62.577%; tC2Q: 0.333, 17.366%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path24

Path Summary:

Slack 2.160
Data Arrival Time 3.985
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_20_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.985 1.222 tNET RR 1 R4C33[2][A] run_cnt_20_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C33[2][A] run_cnt_20_s0/CLK
1.826 0.015 tHld 1 R4C33[2][A] run_cnt_20_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 17.705%; route: 1.456, 66.967%; tC2Q: 0.333, 15.329%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Path25

Path Summary:

Slack 2.160
Data Arrival Time 3.985
Data Required Time 1.826
From u_Reset_Sync/reset_cnt_2_s0
To run_cnt_24_s0
Launch Clk I_clk:[R]
Latch Clk I_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/CLK
2.144 0.333 tC2Q RF 2 R11C30[1][A] u_Reset_Sync/reset_cnt_2_s0/Q
2.379 0.234 tNET FF 1 R11C30[3][B] u_Reset_Sync/sys_resetn_s/I2
2.764 0.385 tINS FR 60 R11C30[3][B] u_Reset_Sync/sys_resetn_s/F
3.985 1.222 tNET RR 1 R4C33[2][B] run_cnt_24_s0/CLEAR

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 I_clk
0.000 0.000 tCL RR 1 IOT13[A] I_clk_ibuf/I
0.844 0.844 tINS RR 97 IOT13[A] I_clk_ibuf/O
1.811 0.966 tNET RR 1 R4C33[2][B] run_cnt_24_s0/CLK
1.826 0.015 tHld 1 R4C33[2][B] run_cnt_24_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%
Arrival Data Path Delay cell: 0.385, 17.705%; route: 1.456, 66.967%; tC2Q: 0.333, 15.329%
Required Clock Path Delay cell: 0.844, 46.631%; route: 0.966, 53.369%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0/CLK

MPW2

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0/CLK

MPW3

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_12_s1

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_12_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_12_s1/CLK

MPW4

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_5_s0/CLK

MPW5

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq1_wptr_0_s0/CLK

MPW6

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq2_wptr_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq2_wptr_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq2_wptr_3_s0/CLK

MPW7

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_9_s0/CLK

MPW8

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_7_s0/CLK

MPW9

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_6_s0/CLK

MPW10

MPW Summary:

Slack: 4.965
Actual Width: 6.215
Required Width: 1.250
Type: Low Pulse Width
Clock: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects: HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].id_reg[16]

Late clock Path:

AT DELAY TYPE RF NODE
6.289 0.000 active clock edge time
6.289 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619 0.330 tCL FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876 0.257 tNET FF HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].id_reg[16]/CLK

Early clock Path:

AT DELAY TYPE RF NODE
12.579 0.000 active clock edge time
12.579 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909 0.330 tCL RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092 0.183 tNET RR HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/read_calibration[0].id_reg[16]/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
629 dma_clk -5.748 0.257
400 ddr_rsti -5.522 2.462
220 pix_clk -4.465 0.257
214 n14_11 -5.748 3.130
120 ch0_vfb_clk_in -3.054 1.078
97 I_clk_d -8.036 2.041
84 XCLK_d 68.273 0.661
78 init_calib_Z -5.748 2.857
69 busy_sr[31] 73.200 2.114
67 reset_r[1] 3.799 1.812

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R8C26 87.50%
R7C11 84.72%
R7C7 83.33%
R18C20 83.33%
R8C16 81.94%
R14C11 81.94%
R14C26 81.94%
R11C20 81.94%
R12C11 81.94%
R8C17 80.56%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name I_clk -period 37.037 -waveform {0 18.518} [get_ports {I_clk}] -add
TC_CLOCK Actived create_clock -name serial_clk -period 2.694 -waveform {0 1.347} [get_nets {serial_clk}] -add
TC_CLOCK Actived create_clock -name pix_clk -period 13.468 -waveform {0 6.734} [get_nets {pix_clk}] -add