Pin Messages

Report Title Pin Report
Design File C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\impl\gwsynthesis\camera_hdmi.vg
Physical Constraints File C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\dk_video.cst
Timing Constraints File C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\dk_video.sdc
Version V1.9.8.09 Education
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Wed Jan 03 23:33:34 2024
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Pin Details

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor BankVccio
I_clk 45/1 Y in IOT13[A] LVCMOS33 NA UP ON NONE NA NA NA NA NA 3.3
I_rst_n 14/3 Y in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
VSYNC 43/1 Y in IOT17[A] LVCMOS33 NA UP ON NONE NA NA NA NA NA 3.3
HREF 42/1 Y in IOT20[B] LVCMOS33 NA UP ON NONE NA NA NA NA NA 3.3
PIXDATA[0] 22/3 Y in IOB22[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
PIXDATA[1] 21/3 Y in IOB16[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
PIXDATA[2] 17/3 Y in IOB6[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
PIXDATA[3] 19/3 Y in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
PIXDATA[4] 20/3 Y in IOB16[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
PIXDATA[5] 18/3 Y in IOB13[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
PIXDATA[6] 16/3 Y in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
PIXDATA[7] 23/3 Y in IOB22[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
PIXDATA[8] 39/1 Y in IOT26[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
PIXDATA[9] 40/1 Y in IOT26[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
PIXCLK 41/1 Y in IOT20[A] LVCMOS33 NA UP ON NONE NA NA NA NA NA 3.3
key 15/3 Y in IOB5[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
O_led[0] 10/0 Y out IOT7[A] LVCMOS33 8 NONE NA NA OFF FAST NA NA NA 3.3
O_led[1] 13/3 N out IOB4[A] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.8
XCLK 33/2 Y out IOR9[B] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
O_tmds_clk_p O_tmds_clk_n 28,27/2 Y out IOR17 LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
O_tmds_data_p[0] O_tmds_data_n[0] 30,29/2 Y out IOR15 LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
O_tmds_data_p[1] O_tmds_data_n[1] 32,31/2 Y out IOR11 LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
O_tmds_data_p[2] O_tmds_data_n[2] 35,34/2 Y out IOR2 LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
SDA 46/1 Y io IOT13[B] LVCMOS33 8 NONE NA NA OFF FAST NA NA NA 3.3
SCL 44/1 Y io IOT17[B] LVCMOS33 8 NONE NA NA OFF FAST NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Slew Rate Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
4/0 - out IOT2[B] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 3.3
6/0 - in IOT3[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
7/0 - in IOT3[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
8/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
9/0 - in IOT5[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
10/0 O_led[0] out IOT7[A] LVCMOS33 8 NONE NA NA OFF FAST NA NA NA 3.3
1/0 - in IOT10[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
2/0 - in IOT10[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
48/1 - in IOT11[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
47/1 - in IOT11[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
45/1 I_clk in IOT13[A] LVCMOS33 NA UP ON NONE NA NA NA NA NA 3.3
46/1 SDA out IOT13[B] LVCMOS33 8 NONE NA NA OFF FAST NA NA NA 3.3
43/1 VSYNC in IOT17[A] LVCMOS33 NA UP ON NONE NA NA NA NA NA 3.3
44/1 SCL out IOT17[B] LVCMOS33 8 NONE NA NA OFF FAST NA NA NA 3.3
41/1 PIXCLK in IOT20[A] LVCMOS33 NA UP ON NONE NA NA NA NA NA 3.3
42/1 HREF in IOT20[B] LVCMOS33 NA UP ON NONE NA NA NA NA NA 3.3
39/1 PIXDATA[8] in IOT26[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
40/1 PIXDATA[9] in IOT26[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 3.3
13/3 O_led[1] out IOB4[A] LVCMOS18 8 NONE NA NA OFF FAST NA NA NA 1.8
14/3 I_rst_n in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
15/3 key in IOB5[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
16/3 PIXDATA[6] in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
17/3 PIXDATA[2] in IOB6[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
18/3 PIXDATA[5] in IOB13[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
19/3 PIXDATA[3] in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
20/3 PIXDATA[4] in IOB16[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
21/3 PIXDATA[1] in IOB16[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
22/3 PIXDATA[0] in IOB22[A] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
23/3 PIXDATA[7] in IOB22[B] LVCMOS18 NA UP ON NONE NA NA NA NA NA 1.8
35/2 O_tmds_data_p[2] out IOR2[A] LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
34/2 O_tmds_data_n[2] out IOR2[B] LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
33/2 XCLK out IOR9[B] LVCMOS25 8 NONE NA NA OFF FAST NA OFF NA 2.5
32/2 O_tmds_data_p[1] out IOR11[A] LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
31/2 O_tmds_data_n[1] out IOR11[B] LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
30/2 O_tmds_data_p[0] out IOR15[A] LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
29/2 O_tmds_data_n[0] out IOR15[B] LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
28/2 O_tmds_clk_p out IOR17[A] LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5
27/2 O_tmds_clk_n out IOR17[B] LVDS25 3.5 NONE NA NA NA NA NA NA NA 2.5