Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\dvi_tx\dvi_tx.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\gowin_pllvr\GW_PLLVR.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\gowin_pllvr\TMDS_PLLVR.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\hyperram_memory_interface\hyperram_memory_interface.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\ov2640\I2C_Interface.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\ov2640\OV2640_Controller.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\ov2640\OV2640_Registers.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\syn_code\syn_gen.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\testpattern.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\video_frame_buffer\video_frame_buffer.v
C:\Users\ChanRa1n\Desktop\TangNano-4K-example-main\camera_hdmi\src\video_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.09 Education
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Wed Jan 03 23:33:28 2024
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module video_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.879s, Peak memory usage = 219.891MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 219.891MB
    Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 219.891MB
    Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.111s, Peak memory usage = 219.891MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 219.891MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 219.891MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 219.891MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 219.891MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 219.891MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 219.891MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 219.891MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.828s, Elapsed time = 0h 0m 0.825s, Peak memory usage = 219.891MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 219.891MB
Generate output files:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 219.891MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 219.891MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 29
Embedded Port 13
I/O Buf 34
    IBUF 12
    OBUF 8
    TBUF 1
    IOBUF 9
    TLVDS_OBUF 4
Register 1111
    DFFE 49
    DFFS 10
    DFFSE 32
    DFFR 3
    DFFP 28
    DFFPE 4
    DFFC 701
    DFFCE 276
    DFFNP 8
LUT 1488
    LUT2 462
    LUT3 364
    LUT4 662
ALU 276
    ALU 276
INV 22
    INV 22
IOLOGIC 34
    IDES4 8
    OSER4 12
    OSER10 4
    IODELAY 10
BSRAM 6
    SDPX9B 5
    pROM 1
CLOCK 5
    CLKDIV 2
    DHCEN 1
    PLLVR 2

Resource Utilization Summary

Resource Usage Utilization
Logic 1786(1510 LUTs, 276 ALUs) / 4608 39%
Register 1111 / 3609 31%
  --Register as Latch 0 / 3609 0%
  --Register as FF 1111 / 3609 31%
BSRAM 6 / 10 60%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_clk Base 37.037 27.0 0.000 18.519 I_clk_ibuf/I
ch0_vfb_clk_in Base 20.000 50.0 0.000 10.000 ch0_vfb_clk_in_s0/F
GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk Generated 6.289 159.0 0.000 3.145 I_clk_ibuf/I I_clk GW_PLLVR_inst/pllvr_inst/CLKOUT
GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk Generated 6.289 159.0 0.000 3.145 I_clk_ibuf/I I_clk GW_PLLVR_inst/pllvr_inst/CLKOUTP
GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk Generated 12.579 79.5 0.000 6.289 I_clk_ibuf/I I_clk GW_PLLVR_inst/pllvr_inst/CLKOUTD
GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk Generated 18.868 53.0 0.000 9.434 I_clk_ibuf/I I_clk GW_PLLVR_inst/pllvr_inst/CLKOUTD3
TMDS_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk Generated 2.694 371.3 0.000 1.347 I_clk_ibuf/I I_clk TMDS_PLLVR_inst/pllvr_inst/CLKOUT
TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk Generated 2.694 371.3 0.000 1.347 I_clk_ibuf/I I_clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTP
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk Generated 80.808 12.4 0.000 40.404 I_clk_ibuf/I I_clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk Generated 8.081 123.8 0.000 4.040 I_clk_ibuf/I I_clk TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3
u_clkdiv/CLKOUT.default_gen_clk Generated 13.468 74.3 0.000 6.734 TMDS_PLLVR_inst/pllvr_inst/CLKOUT TMDS_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk u_clkdiv/CLKOUT
HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk Generated 12.579 79.5 0.000 6.289 GW_PLLVR_inst/pllvr_inst/CLKOUT GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_clk 27.0(MHz) 130.6(MHz) 5 TOP
2 ch0_vfb_clk_in 50.0(MHz) 100.8(MHz) 8 TOP
3 TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk 12.4(MHz) 164.6(MHz) 4 TOP
4 u_clkdiv/CLKOUT.default_gen_clk 74.3(MHz) 61.7(MHz) 12 TOP
5 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk 79.5(MHz) 85.8(MHz) 9 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -4.700
Data Arrival Time 264.633
Data Required Time 259.933
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0
Launch Clk I_clk[R]
Latch Clk ch0_vfb_clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
259.259 0.000 I_clk
259.259 0.000 tCL RR 1 I_clk_ibuf/I
260.241 0.982 tINS RR 97 I_clk_ibuf/O
260.604 0.363 tNET RR 1 key_flag_inst/key_flag_s1/CLK
261.062 0.458 tC2Q RF 4 key_flag_inst/key_flag_s1/Q
261.542 0.480 tNET FF 1 ch0_vfb_de_in_s1/I0
262.574 1.032 tINS FF 1 ch0_vfb_de_in_s1/F
263.054 0.480 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n16_s1/I1
264.153 1.099 tINS FF 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n16_s1/F
264.633 0.480 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
260.000 0.000 ch0_vfb_clk_in
260.000 0.000 tCL RR 120 ch0_vfb_clk_in_s0/F
260.363 0.363 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/CLK
260.333 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0
259.933 -0.400 tSu 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0
Path Statistics:
Clock Skew: -0.982
Setup Relationship: 0.741
Logic Level: 3
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 2.131, 52.887%; route: 1.440, 35.738%; tC2Q: 0.458, 11.375%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack -4.700
Data Arrival Time 264.633
Data Required Time 259.933
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
Launch Clk I_clk[R]
Latch Clk ch0_vfb_clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
259.259 0.000 I_clk
259.259 0.000 tCL RR 1 I_clk_ibuf/I
260.241 0.982 tINS RR 97 I_clk_ibuf/O
260.604 0.363 tNET RR 1 key_flag_inst/key_flag_s1/CLK
261.062 0.458 tC2Q RF 4 key_flag_inst/key_flag_s1/Q
261.542 0.480 tNET FF 1 ch0_vfb_vs_in_s1/I0
262.574 1.032 tINS FF 5 ch0_vfb_vs_in_s1/F
263.054 0.480 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_rising_s0/I1
264.153 1.099 tINS FF 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_rising_s0/F
264.633 0.480 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
260.000 0.000 ch0_vfb_clk_in
260.000 0.000 tCL RR 120 ch0_vfb_clk_in_s0/F
260.363 0.363 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/CLK
260.333 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
259.933 -0.400 tSu 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
Path Statistics:
Clock Skew: -0.982
Setup Relationship: 0.741
Logic Level: 3
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 2.131, 52.887%; route: 1.440, 35.738%; tC2Q: 0.458, 11.375%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack -3.121
Data Arrival Time 263.054
Data Required Time 259.933
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0
Launch Clk I_clk[R]
Latch Clk ch0_vfb_clk_in[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
259.259 0.000 I_clk
259.259 0.000 tCL RR 1 I_clk_ibuf/I
260.241 0.982 tINS RR 97 I_clk_ibuf/O
260.604 0.363 tNET RR 1 key_flag_inst/key_flag_s1/CLK
261.062 0.458 tC2Q RF 4 key_flag_inst/key_flag_s1/Q
261.542 0.480 tNET FF 1 ch0_vfb_vs_in_s1/I0
262.574 1.032 tINS FF 5 ch0_vfb_vs_in_s1/F
263.054 0.480 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
260.000 0.000 ch0_vfb_clk_in
260.000 0.000 tCL RR 120 ch0_vfb_clk_in_s0/F
260.363 0.363 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0/CLK
260.333 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0
259.933 -0.400 tSu 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0
Path Statistics:
Clock Skew: -0.982
Setup Relationship: 0.741
Logic Level: 2
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 1.032, 42.117%; route: 0.960, 39.178%; tC2Q: 0.458, 18.705%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack -2.800
Data Arrival Time 40.832
Data Required Time 38.032
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1
Launch Clk I_clk[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 I_clk_ibuf/I
38.019 0.982 tINS RR 97 I_clk_ibuf/O
38.382 0.363 tNET RR 1 key_flag_inst/key_flag_s1/CLK
38.840 0.458 tC2Q RF 4 key_flag_inst/key_flag_s1/Q
39.320 0.480 tNET FF 1 ch0_vfb_vs_in_s1/I0
40.352 1.032 tINS FF 5 ch0_vfb_vs_in_s1/F
40.832 0.480 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.736 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
38.099 0.363 tCL RR 629 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
38.462 0.363 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1/CLK
38.432 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1
38.032 -0.400 tSu 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1
Path Statistics:
Clock Skew: -0.618
Setup Relationship: 0.699
Logic Level: 2
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 1.032, 42.117%; route: 0.960, 39.178%; tC2Q: 0.458, 18.705%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack -2.800
Data Arrival Time 40.832
Data Required Time 38.032
From key_flag_inst/key_flag_s1
To Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0
Launch Clk I_clk[R]
Latch Clk HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
37.037 0.000 I_clk
37.037 0.000 tCL RR 1 I_clk_ibuf/I
38.019 0.982 tINS RR 97 I_clk_ibuf/O
38.382 0.363 tNET RR 1 key_flag_inst/key_flag_s1/CLK
38.840 0.458 tC2Q RF 4 key_flag_inst/key_flag_s1/Q
39.320 0.480 tNET FF 1 ch0_vfb_vs_in_s1/I0
40.352 1.032 tINS FF 5 ch0_vfb_vs_in_s1/F
40.832 0.480 tNET FF 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.736 0.000 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
38.099 0.363 tCL RR 629 HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
38.462 0.363 tNET RR 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/CLK
38.432 -0.030 tUnc Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0
38.032 -0.400 tSu 1 Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0
Path Statistics:
Clock Skew: -0.618
Setup Relationship: 0.699
Logic Level: 2
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 1.032, 42.117%; route: 0.960, 39.178%; tC2Q: 0.458, 18.705%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%