Intel N3000 PAC开发板 Arria10FPGA 100G智能网卡 支持PCIE程序上传/调试 OpenCL OPAE

近期，从小黄鱼上收了两块N3000的Intel PAC板子，FPGA型号和Microsoft 1768那个差不多，区别是这个支持100G网口，但是DDR4只有9G(组合后为9G)。型号是10AT115S1F45E1SG

先把坑说前面，解决了能减少很多麻烦：

• To compile an AFU using the Intel Quartus® Prime Pro Edition software, your server must have at least 48 GB of system RAM.

• Enable the following options in the BIOS: • Intel VT-x (Intel Virtualization Technology for IA-32 and Intel 64 Processors) • Intel VT-d (Intel Virtualization Technology for Directed I/O)

• 由于该FPGA的规模比较大，如果你用USB Blaster一代的话，烧录一次的时间大概在20分钟，并且只是直接烧录的时间，而不是jif到存储器的双倍时间。这代表着通信带宽比较低，强烈建议更换为USB Blaster II，几秒钟就下载进去了。小梅哥的Blaster二代链接：https://m.tb.cn/h.5f1cv10 99元的二代下载器，需要的自己去买。PS：本站和小梅哥没有任何合作或推广关系。

为啥要收两块？因为我没有100G的网卡。。。最便宜的100G网卡也要一千块。。。况且板卡板载了XL710，实在不行直接连光口输出，就当个2*40G网卡使用也可以。

官网规格：https://www.intel.com/content/www/us/en/products/sku/193920/intel-fpga-pac-n3000/specifications.html

公开资料：https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/legacy-card-support.html?q=N3000&s=Relevancy

使用教程：

• Building an Accelerator Functional Unit for the Intel® FPGA Programmable Acceleration Card N3000

• Intel® FPGA Programmable Acceleration Card N3000 Board Management Controller

• Intel® FPGA Programmable Acceleration Card N3000 Security

• Open Programmable Accelerator Engine (OPAE) Linux Device Driver Architecture

• Open Programmable Acceleration Engine (OPAE) In Depth

• OPAE开源页面

DataSheet：683260.pdf

其他相关文件备份：

• ds-pac-n3000-n-683434-691510 (1).pdf

• ug-ias-n3000-683040-677059.pdf

• ug-ias-n3000-n-683362-677063.pdf

• ug-afu-dev-n3000-683190-677051.pdf

• mnl-ias-ccip-683193-666556.pdf

• ds-nfv-a10-683214-666602.pdf

• vmware_n3000_fpga_management_quick_start_guide.pdf

• MDDSDoc_57868_1.0.pdf

• ug-qs-ias-opencl-a10-ch-683831-677049.pdf

• ug-pac-security-n3000-683519-677057.pdf

• pdn2211.pdf

• ug-pac-bmc-n3000-683709-666828.pdf

• ug-pac-bmc-n3000-n-683186-677053.pdf

• mnl-api-dpdk-n3000-683512-677050.pdf

• readme-n3000-ias-v1-3-1update2.pdf

• rn-ias-n3000-683749-666780.pdf

• ug-qs-ias-opencl-a10-683831-677049.pdf

• rn-ias-n3000-n-683474-677061.pdf

• ug-qs-ias-opencl-a10-v1-0-1-0-production-683633-722138.pdf

• ug-afu-nlb-n3000-683693-666586.pdf

• programmable-devices-64984-declaration-of-conformity.pdf

• programmable-devices-64985-declaration-of-conformity.pdf

• programmable-devices-64975-declaration-of-conformity.pdf

• intel-ifpga-mgmt-tool-utils_1.0.1-1oem.700.1.0.15843807_18225162-package.zip

• intel-ifpga-n3000-mgmt_1.0.9-1oem.700.1.0.15843807_18188203-package.zip

• fpga-platform-selector-guide.pdf

参考链接：https://egallen.com/intel-arria-10-gx-fpga-opae/#test-opencl

可以看到仅QSFP28A可以进行100G通信，另外一个QSFP28B最高只可以进行50G通信，加一块就是150G。

也就是说，可以通过QSFP28接口发送和接收包数据，解析后将其中的部分下传至XL710，也可以进行逻辑操作，比如校验，加解密等高层应用。

但是Pcie3.0单线的最大理论速率为8 * 128 / 130 = 7.877 Gbps，Pcie3.0*16的最大理论速率为7.877 Gbps*16=126.032Gbps。

这代表着，如果你配置QSFP为150G的双口模式，则最多只能透传126G，其实也不算浪费，126四舍五入为125，也就是六分之一的流量可以被用于添加数据头等。

其中，PEX8747也可以修改模式，比如你可以将FPGA侧的2*Pcie*8更换为1*Pcie*16以更容易的进行通信。

同时也支持Pcie 1.0/1.1/2.0，老旧主板也可以用。

通过原理框图可以得知，A10可以通过M10进行配置，也可以通过PCIE直接在线重配置。

PS：其实板载有JTAG接口的，原理图上没写罢了，排针为2.54mm间距，2*5P，在这个位置：

如果需要用JTAG烧写程序，需要把板载的SW2开关拨到OFF。

注意电源接口

1-3P为12V，4-6P为GND，其中5为Sense，即ATX标准接口，并且要求至少150W的电源。

PS：这里的150W指的是Pcie+6Pin一起的要求150W，其实很容易算，Pcie最大输出75W，6Pin最大提供75W，刚刚好是150。建议使用连接了3个12V的6Pin接口，最好是显卡的供电。

所有的A10的板卡的散热，均是非常之惊人，我尝试过更换Microsoft 1768,以及本板卡的散热为散热鳍片+散热风扇，或者涡轮风扇，效果均不理想，原因有二：
1、Chip背面的散热难以解决，这个也是最重要的问题。机箱面积有限，放不了太多的风扇。

2、低风量的风扇压不住，高风量的风扇吵死人，我放机柜扔阳台才能勉强用，太吵了。

值得注意的是，官方环境仅支持Linux，目前我正在移植基于Linux和Windows环境下的OpenCL环境。

另外Quartus Pro 19.2的和谐工具是真的难找，最终在俄罗斯的某论坛找到，你不要找我要，请自己购买正版。仅学习用途，实在不好意思，不能提供。

以下是通过分析Demo工程得到的Pin约束，有了这个就可以很方便的自定义OpenCL Custom Platform。

# PTP Test Points

set_location_assignment PIN_AM33 -to TP_51
set_location_assignment PIN_AN33 -to TP_52
set_location_assignment PIN_AR35 -to TP_53
set_location_assignment PIN_AN34 -to PPS_MAX10

set_instance_assignment -name IO_STANDARD 1.8V -to TP_51
set_instance_assignment -name IO_STANDARD 1.8V -to TP_52
set_instance_assignment -name IO_STANDARD 1.8V -to TP_53
set_instance_assignment -name IO_STANDARD 1.8V -to PPS_MAX10

# PIPE Gen3 x8 interface 0. (GXBL0,1)
set_instance_assignment -name IO_STANDARD HCSL -to pcie0_pipe_gen3_x8_ref_clk
set_location_assignment PIN_AJ37 -to pcie0_pipe_gen3_x8_ref_clk

set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie0_pcie_pins_perst_n
set_location_assignment PIN_BC30 -to pcie0_pcie_pins_perst_n
#set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie0_pipe_gen3_x8_rx_serial[*]
set_location_assignment PIN_AT40 -to pcie0_pipe_gen3_x8_rx_serial[0]
set_location_assignment PIN_AP40 -to pcie0_pipe_gen3_x8_rx_serial[1]
set_location_assignment PIN_AN42 -to pcie0_pipe_gen3_x8_rx_serial[2]
set_location_assignment PIN_AM40 -to pcie0_pipe_gen3_x8_rx_serial[3]
set_location_assignment PIN_AL42 -to pcie0_pipe_gen3_x8_rx_serial[4]
set_location_assignment PIN_AK40 -to pcie0_pipe_gen3_x8_rx_serial[5]
set_location_assignment PIN_AJ42 -to pcie0_pipe_gen3_x8_rx_serial[6]
set_location_assignment PIN_AH40 -to pcie0_pipe_gen3_x8_rx_serial[7]
#set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to pcie0_pipe_gen3_x8_tx_serial[*]
set_location_assignment PIN_BB44 -to pcie0_pipe_gen3_x8_tx_serial[0]
set_location_assignment PIN_BA42 -to pcie0_pipe_gen3_x8_tx_serial[1]
set_location_assignment PIN_AY44 -to pcie0_pipe_gen3_x8_tx_serial[2]
set_location_assignment PIN_AW42 -to pcie0_pipe_gen3_x8_tx_serial[3]
set_location_assignment PIN_AV44 -to pcie0_pipe_gen3_x8_tx_serial[4]
set_location_assignment PIN_AU42 -to pcie0_pipe_gen3_x8_tx_serial[5]
set_location_assignment PIN_AT44 -to pcie0_pipe_gen3_x8_tx_serial[6]
set_location_assignment PIN_AR42 -to pcie0_pipe_gen3_x8_tx_serial[7]


set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_rx_serial[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_rx_serial[2]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_rx_serial[3]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_rx_serial[4]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_rx_serial[5]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_rx_serial[6]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_rx_serial[7]

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_tx_serial[0]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_tx_serial[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_tx_serial[2]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_tx_serial[3]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_tx_serial[4]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_tx_serial[5]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_tx_serial[6]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to pcie0_pipe_gen3_x8_tx_serial[7]


set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie0_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie0_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie0_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to pcie0_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to pcie0_pipe_gen3_x8_rx_serial[0]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie0_pipe_gen3_x8_rx_serial[1]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie0_pipe_gen3_x8_rx_serial[1]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie0_pipe_gen3_x8_rx_serial[1]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie0_pipe_gen3_x8_rx_serial[2]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie0_pipe_gen3_x8_rx_serial[2]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie0_pipe_gen3_x8_rx_serial[2]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie0_pipe_gen3_x8_rx_serial[3]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie0_pipe_gen3_x8_rx_serial[3]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie0_pipe_gen3_x8_rx_serial[3]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie0_pipe_gen3_x8_rx_serial[4]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie0_pipe_gen3_x8_rx_serial[4]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie0_pipe_gen3_x8_rx_serial[4]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie0_pipe_gen3_x8_rx_serial[5]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie0_pipe_gen3_x8_rx_serial[5]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie0_pipe_gen3_x8_rx_serial[5]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie0_pipe_gen3_x8_rx_serial[6]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie0_pipe_gen3_x8_rx_serial[6]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie0_pipe_gen3_x8_rx_serial[6]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie0_pipe_gen3_x8_rx_serial[7]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie0_pipe_gen3_x8_rx_serial[7]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie0_pipe_gen3_x8_rx_serial[7]



#####################################################################
#                             PCIe 1                                #
#####################################################################
if { ! [info exists PCIE1_OFF] } {
set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie1_pcie_pins_perst_n
set_location_assignment PIN_BA27 -to pcie1_pcie_pins_perst_n

set_instance_assignment -name IO_STANDARD HCSL -to pcie1_pipe_gen3_x8_ref_clk
set_location_assignment PIN_AA8 -to pcie1_pipe_gen3_x8_ref_clk

set_location_assignment PIN_AF1 -to pcie1_pipe_gen3_x8_tx_serial[0]
set_location_assignment PIN_AD1 -to pcie1_pipe_gen3_x8_tx_serial[1]
set_location_assignment PIN_AB1 -to pcie1_pipe_gen3_x8_tx_serial[2]
set_location_assignment PIN_Y1  -to pcie1_pipe_gen3_x8_tx_serial[3]
set_location_assignment PIN_V1  -to pcie1_pipe_gen3_x8_tx_serial[4]
set_location_assignment PIN_T1  -to pcie1_pipe_gen3_x8_tx_serial[5]
set_location_assignment PIN_P1  -to pcie1_pipe_gen3_x8_tx_serial[6]
set_location_assignment PIN_M1  -to pcie1_pipe_gen3_x8_tx_serial[7]

set_location_assignment PIN_AC3 -to pcie1_pipe_gen3_x8_rx_serial[0]
set_location_assignment PIN_AB5 -to pcie1_pipe_gen3_x8_rx_serial[1]
set_location_assignment PIN_AA3 -to pcie1_pipe_gen3_x8_rx_serial[2]
set_location_assignment PIN_W3  -to pcie1_pipe_gen3_x8_rx_serial[3]
set_location_assignment PIN_Y5  -to pcie1_pipe_gen3_x8_rx_serial[4]
set_location_assignment PIN_V5  -to pcie1_pipe_gen3_x8_rx_serial[5]
set_location_assignment PIN_U3  -to pcie1_pipe_gen3_x8_rx_serial[6]
set_location_assignment PIN_T5  -to pcie1_pipe_gen3_x8_rx_serial[7]

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_rx_serial[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_rx_serial[2]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_rx_serial[3]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_rx_serial[4]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_rx_serial[5]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_rx_serial[6]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_rx_serial[7]

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_tx_serial[0] 
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_tx_serial[1] 
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_tx_serial[2] 
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_tx_serial[3] 
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_tx_serial[4] 
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_tx_serial[5] 
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_tx_serial[6] 
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie1_pipe_gen3_x8_tx_serial[7] 

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie1_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie1_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie1_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to pcie1_pipe_gen3_x8_rx_serial[0]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to pcie1_pipe_gen3_x8_rx_serial[0]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie1_pipe_gen3_x8_rx_serial[1]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie1_pipe_gen3_x8_rx_serial[1]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie1_pipe_gen3_x8_rx_serial[1]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to pcie1_pipe_gen3_x8_rx_serial[1]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to pcie1_pipe_gen3_x8_rx_serial[1]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie1_pipe_gen3_x8_rx_serial[2]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie1_pipe_gen3_x8_rx_serial[2]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie1_pipe_gen3_x8_rx_serial[2]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to pcie1_pipe_gen3_x8_rx_serial[2]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to pcie1_pipe_gen3_x8_rx_serial[2]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie1_pipe_gen3_x8_rx_serial[3]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie1_pipe_gen3_x8_rx_serial[3]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie1_pipe_gen3_x8_rx_serial[3]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to pcie1_pipe_gen3_x8_rx_serial[3]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to pcie1_pipe_gen3_x8_rx_serial[3]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie1_pipe_gen3_x8_rx_serial[4]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie1_pipe_gen3_x8_rx_serial[4]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie1_pipe_gen3_x8_rx_serial[4]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to pcie1_pipe_gen3_x8_rx_serial[4]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to pcie1_pipe_gen3_x8_rx_serial[4]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie1_pipe_gen3_x8_rx_serial[5]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie1_pipe_gen3_x8_rx_serial[5]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie1_pipe_gen3_x8_rx_serial[5]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to pcie1_pipe_gen3_x8_rx_serial[5]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to pcie1_pipe_gen3_x8_rx_serial[5]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie1_pipe_gen3_x8_rx_serial[6]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie1_pipe_gen3_x8_rx_serial[6]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie1_pipe_gen3_x8_rx_serial[6]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to pcie1_pipe_gen3_x8_rx_serial[6]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to pcie1_pipe_gen3_x8_rx_serial[6]

set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to pcie1_pipe_gen3_x8_rx_serial[7]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to pcie1_pipe_gen3_x8_rx_serial[7]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_7 -to pcie1_pipe_gen3_x8_rx_serial[7]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to pcie1_pipe_gen3_x8_rx_serial[7]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to pcie1_pipe_gen3_x8_rx_serial[7]
}
###########################################################################################################################

set_location_assignment PIN_BB32 -to G_CLK100
set_instance_assignment -name IO_STANDARD LVDS -to G_CLK100
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to G_CLK100

set_location_assignment PIN_BD27 -to FPGA_DEV_CLR_N
set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_DEV_CLR_N

set_location_assignment PIN_AM31 -to FPGA_MISC_RESET_N
set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_MISC_RESET_N

set_location_assignment PIN_BD29 -to BMC_CRC_ERROR
set_instance_assignment -name IO_STANDARD 1.8V -to BMC_CRC_ERROR

set_location_assignment PIN_AN31                                  -to LED_PORT_LINK_25G[0]
set_instance_assignment -name IO_STANDARD 1.8V                    -to LED_PORT_LINK_25G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to LED_PORT_LINK_25G[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to LED_PORT_LINK_25G[0]
set_instance_assignment -name SLEW_RATE 1                         -to LED_PORT_LINK_25G[0]


set_location_assignment PIN_AT34                                  -to LED_PORT_LINK_25G[1]
set_instance_assignment -name IO_STANDARD 1.8V                    -to LED_PORT_LINK_25G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to LED_PORT_LINK_25G[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to LED_PORT_LINK_25G[1]
set_instance_assignment -name SLEW_RATE 1                         -to LED_PORT_LINK_25G[1]


set_location_assignment PIN_BB28                                  -to LED_PORT_LINK_10G[0]
set_instance_assignment -name IO_STANDARD 1.8V                    -to LED_PORT_LINK_10G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to LED_PORT_LINK_10G[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to LED_PORT_LINK_10G[0]
set_instance_assignment -name SLEW_RATE 1                         -to LED_PORT_LINK_10G[0]


set_location_assignment PIN_BB30                                  -to LED_PORT_LINK_10G[1]
set_instance_assignment -name IO_STANDARD 1.8V                    -to LED_PORT_LINK_10G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to LED_PORT_LINK_10G[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to LED_PORT_LINK_10G[1]
set_instance_assignment -name SLEW_RATE 1                         -to LED_PORT_LINK_10G[1]


set_location_assignment PIN_AP31                                  -to LED_PORT_ACTIVE[0]
set_instance_assignment -name IO_STANDARD 1.8V                    -to LED_PORT_ACTIVE[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to LED_PORT_ACTIVE[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to LED_PORT_ACTIVE[0]
set_instance_assignment -name SLEW_RATE 1                         -to LED_PORT_ACTIVE[0]


set_location_assignment PIN_AT35                                  -to LED_PORT_ACTIVE[1]
set_instance_assignment -name IO_STANDARD 1.8V                    -to LED_PORT_ACTIVE[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to LED_PORT_ACTIVE[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to LED_PORT_ACTIVE[1]
set_instance_assignment -name SLEW_RATE 1                         -to LED_PORT_ACTIVE[1]


set_location_assignment PIN_AU32                                  -to FPGA_EE_SCL
set_instance_assignment -name IO_STANDARD 1.8V                    -to FPGA_EE_SCL
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_EE_SCL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to FPGA_EE_SCL
set_instance_assignment -name SLEW_RATE 1                         -to FPGA_EE_SCL

set_location_assignment PIN_AT32                                  -to FPGA_EE_SDA
set_instance_assignment -name IO_STANDARD 1.8V                    -to FPGA_EE_SDA
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_EE_SDA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to FPGA_EE_SDA
set_instance_assignment -name SLEW_RATE 1                         -to FPGA_EE_SDA

set_location_assignment PIN_AL33                                  -to FPGA_QSPI_CLK
set_instance_assignment -name IO_STANDARD 1.8V                    -to FPGA_QSPI_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_QSPI_CLK
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to FPGA_QSPI_CLK
set_instance_assignment -name SLEW_RATE 1                         -to FPGA_QSPI_CLK

set_location_assignment PIN_AL32                                  -to FPGA_QSPI_CS_N
set_instance_assignment -name IO_STANDARD 1.8V                    -to FPGA_QSPI_CS_N
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_QSPI_CS_N
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to FPGA_QSPI_CS_N
set_instance_assignment -name SLEW_RATE 1                         -to FPGA_QSPI_CS_N

set_location_assignment PIN_AL34                                  -to FPGA_QSPI_D0
set_instance_assignment -name IO_STANDARD 1.8V                    -to FPGA_QSPI_D0
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_QSPI_D0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to FPGA_QSPI_D0
set_instance_assignment -name SLEW_RATE 1                         -to FPGA_QSPI_D0

set_location_assignment PIN_AK34                                  -to FPGA_QSPI_D1
set_instance_assignment -name IO_STANDARD 1.8V                    -to FPGA_QSPI_D1
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_QSPI_D1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to FPGA_QSPI_D1
set_instance_assignment -name SLEW_RATE 1                         -to FPGA_QSPI_D1

set_location_assignment PIN_AN30                                  -to FPGA_QSPI_D2
set_instance_assignment -name IO_STANDARD 1.8V                    -to FPGA_QSPI_D2
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_QSPI_D2
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to FPGA_QSPI_D2
set_instance_assignment -name SLEW_RATE 1                         -to FPGA_QSPI_D2

set_location_assignment PIN_AM30                                  -to FPGA_QSPI_D3
set_instance_assignment -name IO_STANDARD 1.8V                    -to FPGA_QSPI_D3
set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_QSPI_D3
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON            -to FPGA_QSPI_D3
set_instance_assignment -name SLEW_RATE 1                         -to FPGA_QSPI_D3

#####################################################################
#                                                                   #
#                           DDR 4 - A                               #
#                                                                   #
#####################################################################
set_location_assignment PIN_F19 -to DDR0123_RZQ

set_location_assignment PIN_G16 -to DDR0123_A[0]
set_location_assignment PIN_G15 -to DDR0123_A[1]
set_location_assignment PIN_E14 -to DDR0123_A[2]
set_location_assignment PIN_F14 -to DDR0123_A[3]
set_location_assignment PIN_F15 -to DDR0123_A[4]
set_location_assignment PIN_E15 -to DDR0123_A[5]
set_location_assignment PIN_E16 -to DDR0123_A[6]
set_location_assignment PIN_E17 -to DDR0123_A[7]
set_location_assignment PIN_H14 -to DDR0123_A[8]
set_location_assignment PIN_H15 -to DDR0123_A[9]
set_location_assignment PIN_F17 -to DDR0123_A[10]
set_location_assignment PIN_G17 -to DDR0123_A[11]
set_location_assignment PIN_E19 -to DDR0123_A[12]
set_location_assignment PIN_E20 -to DDR0123_A[13]
set_location_assignment PIN_F20 -to DDR0123_A[14]
set_location_assignment PIN_H19 -to DDR0123_A[15]
set_location_assignment PIN_H18 -to DDR0123_A[16]
set_location_assignment PIN_M17 -to DDR0123_ACT_N
set_location_assignment PIN_L25 -to DDR0123_ALERT_N
set_location_assignment PIN_H21 -to DDR0123_BA[0]
set_location_assignment PIN_H20 -to DDR0123_BA[1]
set_location_assignment PIN_G20 -to DDR0123_BG[0]
set_location_assignment PIN_J16 -to DDR0123_CK_N
set_location_assignment PIN_H16 -to DDR0123_CK
set_location_assignment PIN_J18 -to DDR0123_PAR
set_location_assignment PIN_L18 -to DDR01_CKE
set_location_assignment PIN_M16 -to DDR01_CS_N
set_location_assignment PIN_J24 -to DDR0_LDBI_N
set_location_assignment PIN_E24 -to DDR0_UDBI_N
set_location_assignment PIN_A22 -to DDR1_LDBI_N
set_location_assignment PIN_D21 -to DDR1_UDBI_N
set_location_assignment PIN_K25 -to DDR0_DQ[0]
set_location_assignment PIN_J23 -to DDR0_DQ[1]
set_location_assignment PIN_K26 -to DDR0_DQ[2]
set_location_assignment PIN_L23 -to DDR0_DQ[3]
set_location_assignment PIN_L27 -to DDR0_DQ[4]
set_location_assignment PIN_J26 -to DDR0_DQ[5]
set_location_assignment PIN_L28 -to DDR0_DQ[6]
set_location_assignment PIN_M23 -to DDR0_DQ[7]
set_location_assignment PIN_G23 -to DDR0_DQ[8]
set_location_assignment PIN_E21 -to DDR0_DQ[9]
set_location_assignment PIN_H23 -to DDR0_DQ[10]
set_location_assignment PIN_E22 -to DDR0_DQ[11]
set_location_assignment PIN_F24 -to DDR0_DQ[12]
set_location_assignment PIN_F22 -to DDR0_DQ[13]
set_location_assignment PIN_H24 -to DDR0_DQ[14]
set_location_assignment PIN_G22 -to DDR0_DQ[15]
set_location_assignment PIN_C19 -to DDR1_DQ[0]
set_location_assignment PIN_B21 -to DDR1_DQ[1]
set_location_assignment PIN_C20 -to DDR1_DQ[2]
set_location_assignment PIN_B20 -to DDR1_DQ[3]
set_location_assignment PIN_C18 -to DDR1_DQ[4]
set_location_assignment PIN_B22 -to DDR1_DQ[5]
set_location_assignment PIN_D19 -to DDR1_DQ[6]
set_location_assignment PIN_C21 -to DDR1_DQ[7]
set_location_assignment PIN_D24 -to DDR1_DQ[8]
set_location_assignment PIN_A25 -to DDR1_DQ[9]
set_location_assignment PIN_C23 -to DDR1_DQ[10]
set_location_assignment PIN_C24 -to DDR1_DQ[11]
set_location_assignment PIN_D22 -to DDR1_DQ[12]
set_location_assignment PIN_A24 -to DDR1_DQ[13]
set_location_assignment PIN_B23 -to DDR1_DQ[14]
set_location_assignment PIN_A23 -to DDR1_DQ[15]
set_location_assignment PIN_K24 -to DDR0_DQSL_N
set_location_assignment PIN_L24 -to DDR0_DQSL
set_location_assignment PIN_E25 -to DDR0_DQSU_N
set_location_assignment PIN_F25 -to DDR0_DQSU
set_location_assignment PIN_A19 -to DDR1_DQSL_N
set_location_assignment PIN_A20 -to DDR1_DQSL
set_location_assignment PIN_B25 -to DDR1_DQSU_N
set_location_assignment PIN_C25 -to DDR1_DQSU
set_location_assignment PIN_K16 -to DDR01_ODT

set_location_assignment PIN_J22 -to DDR23_CKE
set_location_assignment PIN_M21 -to DDR23_CS_N
set_location_assignment PIN_F13 -to DDR2_LDBI_N
set_location_assignment PIN_J11 -to DDR2_UDBI_N
set_location_assignment PIN_D13 -to DDR3_LDBI_N
set_location_assignment PIN_A14 -to DDR3_UDBI_N
set_location_assignment PIN_G12 -to DDR2_DQ[0]
set_location_assignment PIN_E12 -to DDR2_DQ[1]
set_location_assignment PIN_H11 -to DDR2_DQ[2]
set_location_assignment PIN_E10 -to DDR2_DQ[3]
set_location_assignment PIN_H10 -to DDR2_DQ[4]
set_location_assignment PIN_E11 -to DDR2_DQ[5]
set_location_assignment PIN_G13 -to DDR2_DQ[6]
set_location_assignment PIN_F12 -to DDR2_DQ[7]
set_location_assignment PIN_K11 -to DDR2_DQ[8]
set_location_assignment PIN_K14 -to DDR2_DQ[9]
set_location_assignment PIN_K12 -to DDR2_DQ[10]
set_location_assignment PIN_J13 -to DDR2_DQ[11]
set_location_assignment PIN_L13 -to DDR2_DQ[12]
set_location_assignment PIN_H13 -to DDR2_DQ[13]
set_location_assignment PIN_M12 -to DDR2_DQ[14]
set_location_assignment PIN_J14 -to DDR2_DQ[15]
set_location_assignment PIN_D12 -to DDR3_DQ[0]
set_location_assignment PIN_B13 -to DDR3_DQ[1]
set_location_assignment PIN_C13 -to DDR3_DQ[2]
set_location_assignment PIN_B12 -to DDR3_DQ[3]
set_location_assignment PIN_C10 -to DDR3_DQ[4]
set_location_assignment PIN_A13 -to DDR3_DQ[5]
set_location_assignment PIN_D11 -to DDR3_DQ[6]
set_location_assignment PIN_A12 -to DDR3_DQ[7]
set_location_assignment PIN_A15 -to DDR3_DQ[8]
set_location_assignment PIN_D17 -to DDR3_DQ[9]
set_location_assignment PIN_C15 -to DDR3_DQ[10]
set_location_assignment PIN_B17 -to DDR3_DQ[11]
set_location_assignment PIN_B15 -to DDR3_DQ[12]
set_location_assignment PIN_D16 -to DDR3_DQ[13]
set_location_assignment PIN_C16 -to DDR3_DQ[14]
set_location_assignment PIN_A17 -to DDR3_DQ[15]
set_location_assignment PIN_F10 -to DDR2_DQSL_N
set_location_assignment PIN_G10 -to DDR2_DQSL
set_location_assignment PIN_L14 -to DDR2_DQSU_N
set_location_assignment PIN_M13 -to DDR2_DQSU
set_location_assignment PIN_D14 -to DDR3_DQSL_N
set_location_assignment PIN_C14 -to DDR3_DQSL
set_location_assignment PIN_B18 -to DDR3_DQSU_N
set_location_assignment PIN_A18 -to DDR3_DQSU
set_location_assignment PIN_L20 -to DDR23_ODT

set_location_assignment PIN_G18 -to DDR0123_REFCLK
set_location_assignment PIN_L15 -to DDR0123_RESET_N

#####################################################################
#                                                                   #
#                           DDR 4 - B                               #
#                                                                   #
#####################################################################
set_location_assignment PIN_AY15 -to DDR4567_RZQ

set_location_assignment PIN_AV20 -to DDR4567_A[0]
set_location_assignment PIN_AU20 -to DDR4567_A[1]
set_location_assignment PIN_AV19 -to DDR4567_A[2]
set_location_assignment PIN_AW19 -to DDR4567_A[3]
set_location_assignment PIN_AU21 -to DDR4567_A[4]
set_location_assignment PIN_AV21 -to DDR4567_A[5]
set_location_assignment PIN_AW21 -to DDR4567_A[6]
set_location_assignment PIN_AY21 -to DDR4567_A[7]
set_location_assignment PIN_AW18 -to DDR4567_A[8]
set_location_assignment PIN_AV18 -to DDR4567_A[9]
set_location_assignment PIN_AY20 -to DDR4567_A[10]
set_location_assignment PIN_AY19 -to DDR4567_A[11]
set_location_assignment PIN_AY14 -to DDR4567_A[12]
set_location_assignment PIN_AV16 -to DDR4567_A[13]
set_location_assignment PIN_AU16 -to DDR4567_A[14]
set_location_assignment PIN_AY16 -to DDR4567_A[15]
set_location_assignment PIN_AW16 -to DDR4567_A[16]
set_location_assignment PIN_AR19 -to DDR4567_ACT_N
set_location_assignment PIN_BA12 -to DDR4567_ALERT_N
set_location_assignment PIN_AW14 -to DDR4567_BA[0]
set_location_assignment PIN_AY17 -to DDR4567_BA[1]
set_location_assignment PIN_AW17 -to DDR4567_BG[0]
set_location_assignment PIN_AR21 -to DDR4567_CK_N
set_location_assignment PIN_AP21 -to DDR4567_CK
set_location_assignment PIN_AT20 -to DDR4567_PAR
set_location_assignment PIN_AP18 -to DDR45_CKE
set_location_assignment PIN_AR20 -to DDR45_CS_N
set_location_assignment PIN_BC13 -to DDR4_LDBI_N
set_location_assignment PIN_BB18 -to DDR4_UDBI_N
set_location_assignment PIN_AW13 -to DDR5_LDBI_N
set_location_assignment PIN_AR9 -to DDR5_UDBI_N
set_location_assignment PIN_BB10 -to DDR4_DQ[0]
set_location_assignment PIN_BD13 -to DDR4_DQ[1]
set_location_assignment PIN_BD12 -to DDR4_DQ[2]
set_location_assignment PIN_BD14 -to DDR4_DQ[3]
set_location_assignment PIN_BA10 -to DDR4_DQ[4]
set_location_assignment PIN_BC14 -to DDR4_DQ[5]
set_location_assignment PIN_BB13 -to DDR4_DQ[6]
set_location_assignment PIN_BA13 -to DDR4_DQ[7]
set_location_assignment PIN_BA14 -to DDR4_DQ[8]
set_location_assignment PIN_BD16 -to DDR4_DQ[9]
set_location_assignment PIN_BB16 -to DDR4_DQ[10]
set_location_assignment PIN_BC16 -to DDR4_DQ[11]
set_location_assignment PIN_BA15 -to DDR4_DQ[12]
set_location_assignment PIN_BD17 -to DDR4_DQ[13]
set_location_assignment PIN_BD18 -to DDR4_DQ[14]
set_location_assignment PIN_BC18 -to DDR4_DQ[15]
set_location_assignment PIN_AU10 -to DDR5_DQ[0]
set_location_assignment PIN_AW11 -to DDR5_DQ[1]
set_location_assignment PIN_AY11 -to DDR5_DQ[2]
set_location_assignment PIN_AV13 -to DDR5_DQ[3]
set_location_assignment PIN_AY10 -to DDR5_DQ[4]
set_location_assignment PIN_AV11 -to DDR5_DQ[5]
set_location_assignment PIN_AV10 -to DDR5_DQ[6]
set_location_assignment PIN_AU12 -to DDR5_DQ[7]
set_location_assignment PIN_AT10 -to DDR5_DQ[8]
set_location_assignment PIN_AU13 -to DDR5_DQ[9]
set_location_assignment PIN_AT9 -to DDR5_DQ[10]
set_location_assignment PIN_AP13 -to DDR5_DQ[11]
set_location_assignment PIN_AU8 -to DDR5_DQ[12]
set_location_assignment PIN_AT13 -to DDR5_DQ[13]
set_location_assignment PIN_AT8 -to DDR5_DQ[14]
set_location_assignment PIN_AP14 -to DDR5_DQ[15]
set_location_assignment PIN_BB11 -to DDR4_DQSL_N
set_location_assignment PIN_BB12 -to DDR4_DQSL
set_location_assignment PIN_BC15 -to DDR4_DQSU_N
set_location_assignment PIN_BB15 -to DDR4_DQSU
set_location_assignment PIN_AY12 -to DDR5_DQSL_N
set_location_assignment PIN_AW12 -to DDR5_DQSL
set_location_assignment PIN_AR12 -to DDR5_DQSU_N
set_location_assignment PIN_AP12 -to DDR5_DQSU
set_location_assignment PIN_AN20 -to DDR45_ODT

set_location_assignment PIN_AR17 -to DDR67_CKE
set_location_assignment PIN_AR15 -to DDR67_CS_N
set_location_assignment PIN_BD21 -to DDR6_LDBI_N
set_location_assignment PIN_BD26 -to DDR6_UDBI_N
set_location_assignment PIN_AR25 -to DDR7_LDBI_N
set_location_assignment PIN_AY22 -to DDR7_UDBI_N
set_location_assignment PIN_BD19 -to DDR6_DQ[0]
set_location_assignment PIN_BD22 -to DDR6_DQ[1]
set_location_assignment PIN_BC20 -to DDR6_DQ[2]
set_location_assignment PIN_BC21 -to DDR6_DQ[3]
set_location_assignment PIN_BB20 -to DDR6_DQ[4]
set_location_assignment PIN_BB21 -to DDR6_DQ[5]
set_location_assignment PIN_BA20 -to DDR6_DQ[6]
set_location_assignment PIN_BA19 -to DDR6_DQ[7]
set_location_assignment PIN_BD23 -to DDR6_DQ[8]
set_location_assignment PIN_BB25 -to DDR6_DQ[9]
set_location_assignment PIN_BC23 -to DDR6_DQ[10]
set_location_assignment PIN_BC24 -to DDR6_DQ[11]
set_location_assignment PIN_BB22 -to DDR6_DQ[12]
set_location_assignment PIN_BC25 -to DDR6_DQ[13]
set_location_assignment PIN_BA22 -to DDR6_DQ[14]
set_location_assignment PIN_BC26 -to DDR6_DQ[15]
set_location_assignment PIN_AT23 -to DDR7_DQ[0]
set_location_assignment PIN_AR26 -to DDR7_DQ[1]
set_location_assignment PIN_AT24 -to DDR7_DQ[2]
set_location_assignment PIN_AP26 -to DDR7_DQ[3]
set_location_assignment PIN_AU23 -to DDR7_DQ[4]
set_location_assignment PIN_AP23 -to DDR7_DQ[5]
set_location_assignment PIN_AU22 -to DDR7_DQ[6]
set_location_assignment PIN_AP22 -to DDR7_DQ[7]
set_location_assignment PIN_AY25 -to DDR7_DQ[8]
set_location_assignment PIN_AU25 -to DDR7_DQ[9]
set_location_assignment PIN_BA24 -to DDR7_DQ[10]
set_location_assignment PIN_AV25 -to DDR7_DQ[11]
set_location_assignment PIN_AY24 -to DDR7_DQ[12]
set_location_assignment PIN_AV24 -to DDR7_DQ[13]
set_location_assignment PIN_AW22 -to DDR7_DQ[14]
set_location_assignment PIN_BA25 -to DDR7_DQ[15]
set_location_assignment PIN_BA18 -to DDR6_DQSL_N
set_location_assignment PIN_BA17 -to DDR6_DQSL
set_location_assignment PIN_BA23 -to DDR6_DQSU_N
set_location_assignment PIN_BB23 -to DDR6_DQSU
set_location_assignment PIN_AP24 -to DDR7_DQSL_N
set_location_assignment PIN_AR24 -to DDR7_DQSL
set_location_assignment PIN_AV23 -to DDR7_DQSU_N
set_location_assignment PIN_AW23 -to DDR7_DQSU
set_location_assignment PIN_AT14 -to DDR67_ODT

set_location_assignment PIN_AV15 -to DDR4567_REFCLK
set_location_assignment PIN_AT22 -to DDR4567_RESET_N

#####################################################################
#                                                                   #
#                           DDR 4 - C                               #
#                                                                   #
#####################################################################
set_location_assignment PIN_AE14 -to DDR8_RZQ

set_location_assignment PIN_AM17 -to DDR8_A[0]
set_location_assignment PIN_AL17 -to DDR8_A[1]
set_location_assignment PIN_AL19 -to DDR8_A[2]
set_location_assignment PIN_AL20 -to DDR8_A[3]
set_location_assignment PIN_AM15 -to DDR8_A[4]
set_location_assignment PIN_AL14 -to DDR8_A[5]
set_location_assignment PIN_AM16 -to DDR8_A[6]
set_location_assignment PIN_AN16 -to DDR8_A[7]
set_location_assignment PIN_AL15 -to DDR8_A[8]
set_location_assignment PIN_AK15 -to DDR8_A[9]
set_location_assignment PIN_AM18 -to DDR8_A[10]
set_location_assignment PIN_AL18 -to DDR8_A[11]
set_location_assignment PIN_AE15 -to DDR8_A[12]
set_location_assignment PIN_AE11 -to DDR8_A[13]
set_location_assignment PIN_AD12 -to DDR8_A[14]
set_location_assignment PIN_AF14 -to DDR8_A[15]
set_location_assignment PIN_AF15 -to DDR8_A[16]
set_location_assignment PIN_AR10 -to DDR8_ACT_N
set_location_assignment PIN_AJ12 -to DDR8_ALERT_N
set_location_assignment PIN_AG11 -to DDR8_BA[0]
set_location_assignment PIN_AF12 -to DDR8_BA[1]
set_location_assignment PIN_AE12 -to DDR8_BG
set_location_assignment PIN_AK11 -to DDR8_CK_N
set_location_assignment PIN_AL10 -to DDR8_CK
set_location_assignment PIN_AN13 -to DDR8_CKE
set_location_assignment PIN_AP11 -to DDR8_CS_N
set_location_assignment PIN_AJ11 -to DDR8_DBI_N[0]
set_location_assignment PIN_W12 -to DDR8_DBI_N[1]
set_location_assignment PIN_AK12 -to DDR8_DQ[0]
set_location_assignment PIN_AH10 -to DDR8_DQ[1]
set_location_assignment PIN_AL12 -to DDR8_DQ[2]
set_location_assignment PIN_AH11 -to DDR8_DQ[3]
set_location_assignment PIN_AL13 -to DDR8_DQ[4]
set_location_assignment PIN_AJ13 -to DDR8_DQ[5]
set_location_assignment PIN_AK14 -to DDR8_DQ[6]
set_location_assignment PIN_AJ14 -to DDR8_DQ[7]
set_location_assignment PIN_Y14 -to DDR8_DQ[8]
set_location_assignment PIN_U12 -to DDR8_DQ[9]
set_location_assignment PIN_W13 -to DDR8_DQ[10]
set_location_assignment PIN_T10 -to DDR8_DQ[11]
set_location_assignment PIN_Y15 -to DDR8_DQ[12]
set_location_assignment PIN_U11 -to DDR8_DQ[13]
set_location_assignment PIN_W11 -to DDR8_DQ[14]
set_location_assignment PIN_T12 -to DDR8_DQ[15]
set_location_assignment PIN_AH14 -to DDR8_LDQS_N
set_location_assignment PIN_AH13 -to DDR8_LDQS
set_location_assignment PIN_W10 -to DDR8_UDQS_N
set_location_assignment PIN_V11 -to DDR8_UDQS
set_location_assignment PIN_AN15 -to DDR8_ODT
set_location_assignment PIN_AN10 -to DDR8_PAR

set_location_assignment PIN_AF13 -to DDR8_REFCLK
set_location_assignment PIN_AM11 -to DDR8_RESET_N

#####################################################################
#                                                                   #
#                             QDDR 4                                #
#                                                                   #
#####################################################################
set_location_assignment PIN_J34 -to QDR0_RZQ

set_location_assignment PIN_T32 -to QDR0_A[0]
set_location_assignment PIN_M32 -to QDR0_A[1]
set_location_assignment PIN_L32 -to QDR0_A[2]
set_location_assignment PIN_N34 -to QDR0_A[3]
set_location_assignment PIN_M35 -to QDR0_A[4]
set_location_assignment PIN_L34 -to QDR0_A[5]
set_location_assignment PIN_K34 -to QDR0_A[6]
set_location_assignment PIN_M33 -to QDR0_A[7]
set_location_assignment PIN_L33 -to QDR0_A[8]
set_location_assignment PIN_J33 -to QDR0_A[9]
set_location_assignment PIN_J32 -to QDR0_A[10]
set_location_assignment PIN_H31 -to QDR0_A[11]
set_location_assignment PIN_J31 -to QDR0_A[12]
set_location_assignment PIN_H34 -to QDR0_A[13]
set_location_assignment PIN_H33 -to QDR0_A[14]
set_location_assignment PIN_G32 -to QDR0_A[15]
set_location_assignment PIN_E32 -to QDR0_A[16]
set_location_assignment PIN_F32 -to QDR0_A[17]
set_location_assignment PIN_G33 -to QDR0_A[18]
set_location_assignment PIN_F33 -to QDR0_A[19]
set_location_assignment PIN_G35 -to QDR0_A[20]
set_location_assignment PIN_H35 -to QDR0_A[21]
set_location_assignment PIN_E35 -to QDR0_A[22]
set_location_assignment PIN_E34 -to QDR0_A[23]
set_location_assignment PIN_C35 -to QDR0_A[24]
set_location_assignment PIN_U32 -to QDR0_AINV

set_location_assignment PIN_T34 -to QDR0_CFG_N
set_location_assignment PIN_R31 -to QDR0_CK_N
set_location_assignment PIN_R30 -to QDR0_CK
set_location_assignment PIN_G26 -to QDR0_DINVA[0]
set_location_assignment PIN_A28 -to QDR0_DINVA[1]
set_location_assignment PIN_AG31 -to QDR0_DINVB[0]
set_location_assignment PIN_Y31 -to QDR0_DINVB[1]
set_location_assignment PIN_E31 -to QDR0_DKA_N[0]
set_location_assignment PIN_E30 -to QDR0_DKA[0]
set_location_assignment PIN_B30 -to QDR0_DKA_N[1]
set_location_assignment PIN_B31 -to QDR0_DKA[1]
set_location_assignment PIN_Y34 -to QDR0_DKB_N[0]
set_location_assignment PIN_W34 -to QDR0_DKB[0]
set_location_assignment PIN_Y35 -to QDR0_DKB_N[1]
set_location_assignment PIN_W35 -to QDR0_DKB[1]
set_location_assignment PIN_F28 -to QDR0_DQA[0]
set_location_assignment PIN_H26 -to QDR0_DQA[1]
set_location_assignment PIN_G27 -to QDR0_DQA[2]
set_location_assignment PIN_G28 -to QDR0_DQA[3]
set_location_assignment PIN_J28 -to QDR0_DQA[4]
set_location_assignment PIN_F27 -to QDR0_DQA[5]
set_location_assignment PIN_K27 -to QDR0_DQA[6]
set_location_assignment PIN_H25 -to QDR0_DQA[7]
set_location_assignment PIN_G25 -to QDR0_DQA[8]
set_location_assignment PIN_B27 -to QDR0_DQA[9]
set_location_assignment PIN_A27 -to QDR0_DQA[10]
set_location_assignment PIN_B28 -to QDR0_DQA[11]
set_location_assignment PIN_D28 -to QDR0_DQA[12]
set_location_assignment PIN_C28 -to QDR0_DQA[13]
set_location_assignment PIN_E26 -to QDR0_DQA[14]
set_location_assignment PIN_E27 -to QDR0_DQA[15]
set_location_assignment PIN_D26 -to QDR0_DQA[16]
set_location_assignment PIN_D27 -to QDR0_DQA[17]
set_location_assignment PIN_AG32 -to QDR0_DQB[0]
set_location_assignment PIN_AG33 -to QDR0_DQB[1]
set_location_assignment PIN_AF32 -to QDR0_DQB[2]
set_location_assignment PIN_AE30 -to QDR0_DQB[3]
set_location_assignment PIN_AE32 -to QDR0_DQB[4]
set_location_assignment PIN_AE31 -to QDR0_DQB[5]
set_location_assignment PIN_AF30 -to QDR0_DQB[6]
set_location_assignment PIN_AH31 -to QDR0_DQB[7]
set_location_assignment PIN_AH33 -to QDR0_DQB[8]
set_location_assignment PIN_AC31 -to QDR0_DQB[9]
set_location_assignment PIN_W31 -to QDR0_DQB[10]
set_location_assignment PIN_AD31 -to QDR0_DQB[11]
set_location_assignment PIN_AB32 -to QDR0_DQB[12]
set_location_assignment PIN_Y30 -to QDR0_DQB[13]
set_location_assignment PIN_AD33 -to QDR0_DQB[14]
set_location_assignment PIN_AA30 -to QDR0_DQB[15]
set_location_assignment PIN_AD32 -to QDR0_DQB[16]
set_location_assignment PIN_AB31 -to QDR0_DQB[17]
set_location_assignment PIN_R34 -to QDR0_LBK0_N
set_location_assignment PIN_P34 -to QDR0_LBK1_N
set_location_assignment PIN_N33 -to QDR0_LDA_N
set_location_assignment PIN_P33 -to QDR0_LDB_N

set_location_assignment PIN_J27 -to QDR0_QKA_N[0]
set_location_assignment PIN_H28 -to QDR0_QKA[0]
set_location_assignment PIN_C26 -to QDR0_QKA_N[1]
set_location_assignment PIN_B26 -to QDR0_QKA[1]
set_location_assignment PIN_AJ32 -to QDR0_QKB_N[0]
set_location_assignment PIN_AJ31 -to QDR0_QKB[0]
set_location_assignment PIN_Y32 -to QDR0_QKB_N[1]
set_location_assignment PIN_AA32 -to QDR0_QKB[1]

set_location_assignment PIN_F34 -to QDR0_REFCLK
set_location_assignment PIN_T35 -to QDR0_RST_N
set_location_assignment PIN_U33 -to QDR0_RWA_N
set_location_assignment PIN_T33 -to QDR0_RWB_N

#############################################################################################
# QSFP A ####################################################################################
set_instance_assignment -name IO_STANDARD LVDS -to FPGA_QSA_REFCLK_P
set_location_assignment PIN_N37 -to FPGA_QSA_REFCLK_P

set_location_assignment PIN_R42 -to QSFPA_RT_RXP_0
set_location_assignment PIN_P40 -to QSFPA_RT_RXP_1
set_location_assignment PIN_D40 -to QSFPA_RT_RXP_2
set_location_assignment PIN_E38 -to QSFPA_RT_RXP_3
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPA_RT_RXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPA_RT_RXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPA_RT_RXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPA_RT_RXP_3
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPA_RT_RXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPA_RT_RXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPA_RT_RXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPA_RT_RXP_3

set_location_assignment PIN_K44 -to QSFPA_RT_TXP_0
set_location_assignment PIN_J42 -to QSFPA_RT_TXP_1
set_location_assignment PIN_B40 -to QSFPA_RT_TXP_2
set_location_assignment PIN_A42 -to QSFPA_RT_TXP_3
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPA_RT_TXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPA_RT_TXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPA_RT_TXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPA_RT_TXP_3
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPA_RT_TXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPA_RT_TXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPA_RT_TXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPA_RT_TXP_3

# QSFP B ######################################################################################
set_instance_assignment -name IO_STANDARD LVDS -to FPGA_QSB_REFCLK_P
set_location_assignment PIN_AE37 -to FPGA_QSB_REFCLK_P

set_location_assignment PIN_AD40 -to QSFPB_RT_RXP_0
set_location_assignment PIN_AC42 -to QSFPB_RT_RXP_1
set_location_assignment PIN_AG42 -to QSFPB_RT_RXP_2
set_location_assignment PIN_AF40 -to QSFPB_RT_RXP_3
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPB_RT_RXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPB_RT_RXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPB_RT_RXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPB_RT_RXP_3
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPB_RT_RXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPB_RT_RXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPB_RT_RXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPB_RT_RXP_3

set_location_assignment PIN_AH44 -to QSFPB_RT_TXP_0
set_location_assignment PIN_AF44 -to QSFPB_RT_TXP_1
set_location_assignment PIN_AP44 -to QSFPB_RT_TXP_2
set_location_assignment PIN_AM44 -to QSFPB_RT_TXP_3
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPB_RT_TXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPB_RT_TXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPB_RT_TXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to QSFPB_RT_TXP_3
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPB_RT_TXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPB_RT_TXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPB_RT_TXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to QSFPB_RT_TXP_3

# XL1A ######################################################################################
set_instance_assignment -name IO_STANDARD LVDS -to FPGA_XL1_REFCLK_P
set_location_assignment PIN_N8 -to FPGA_XL1_REFCLK_P

set_location_assignment PIN_M5 -to FPGA_XL1A_RT_RXP_0
set_location_assignment PIN_N3 -to FPGA_XL1A_RT_RXP_1
set_location_assignment PIN_P5 -to FPGA_XL1A_RT_RXP_2
set_location_assignment PIN_R3 -to FPGA_XL1A_RT_RXP_3
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1A_RT_RXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1A_RT_RXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1A_RT_RXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1A_RT_RXP_3
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1A_RT_RXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1A_RT_RXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1A_RT_RXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1A_RT_RXP_3

set_location_assignment PIN_G3 -to FPGA_XL1A_RT_TXP_0
set_location_assignment PIN_H1 -to FPGA_XL1A_RT_TXP_1
set_location_assignment PIN_J3 -to FPGA_XL1A_RT_TXP_2
set_location_assignment PIN_K1 -to FPGA_XL1A_RT_TXP_3
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1A_RT_TXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1A_RT_TXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1A_RT_TXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1A_RT_TXP_3
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1A_RT_TXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1A_RT_TXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1A_RT_TXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1A_RT_TXP_3

# XL1B ######################################################################################
set_location_assignment PIN_E7 -to FPGA_XL1B_RT_RXP_0
set_location_assignment PIN_F5 -to FPGA_XL1B_RT_RXP_1
set_location_assignment PIN_G7 -to FPGA_XL1B_RT_RXP_2
set_location_assignment PIN_H5 -to FPGA_XL1B_RT_RXP_3

set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1B_RT_RXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1B_RT_RXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1B_RT_RXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1B_RT_RXP_3

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1B_RT_RXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1B_RT_RXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1B_RT_RXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1B_RT_RXP_3

set_location_assignment PIN_A3 -to FPGA_XL1B_RT_TXP_0
set_location_assignment PIN_B1 -to FPGA_XL1B_RT_TXP_1
set_location_assignment PIN_C3 -to FPGA_XL1B_RT_TXP_2
set_location_assignment PIN_D1 -to FPGA_XL1B_RT_TXP_3

set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1B_RT_TXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1B_RT_TXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1B_RT_TXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL1B_RT_TXP_3

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1B_RT_TXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1B_RT_TXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1B_RT_TXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL1B_RT_TXP_3

# XL2A ######################################################################################
set_instance_assignment -name IO_STANDARD LVDS -to FPGA_XL2_REFCLK_P
set_location_assignment PIN_AJ8 -to FPGA_XL2_REFCLK_P

set_location_assignment PIN_AM5 -to FPGA_XL2A_RT_RXP_0
set_location_assignment PIN_AN3 -to FPGA_XL2A_RT_RXP_1
set_location_assignment PIN_AP5 -to FPGA_XL2A_RT_RXP_2
set_location_assignment PIN_AT5 -to FPGA_XL2A_RT_RXP_3
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2A_RT_RXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2A_RT_RXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2A_RT_RXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2A_RT_RXP_3
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2A_RT_RXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2A_RT_RXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2A_RT_RXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2A_RT_RXP_3

set_location_assignment PIN_AW3 -to FPGA_XL2A_RT_TXP_0
set_location_assignment PIN_AY1 -to FPGA_XL2A_RT_TXP_1
set_location_assignment PIN_BA3 -to FPGA_XL2A_RT_TXP_2
set_location_assignment PIN_BB1 -to FPGA_XL2A_RT_TXP_3
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2A_RT_TXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2A_RT_TXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2A_RT_TXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2A_RT_TXP_3
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2A_RT_TXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2A_RT_TXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2A_RT_TXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2A_RT_TXP_3

# XL2B ######################################################################################
set_location_assignment PIN_AH5 -to FPGA_XL2B_RT_RXP_0
set_location_assignment PIN_AJ3 -to FPGA_XL2B_RT_RXP_1
set_location_assignment PIN_AK5 -to FPGA_XL2B_RT_RXP_2
set_location_assignment PIN_AL3 -to FPGA_XL2B_RT_RXP_3

set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2B_RT_RXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2B_RT_RXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2B_RT_RXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2B_RT_RXP_3

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2B_RT_RXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2B_RT_RXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2B_RT_RXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2B_RT_RXP_3

set_location_assignment PIN_AR3 -to FPGA_XL2B_RT_TXP_0
set_location_assignment PIN_AT1 -to FPGA_XL2B_RT_TXP_1
set_location_assignment PIN_AU3 -to FPGA_XL2B_RT_TXP_2
set_location_assignment PIN_AV1 -to FPGA_XL2B_RT_TXP_3

set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2B_RT_TXP_0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2B_RT_TXP_1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2B_RT_TXP_2
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FPGA_XL2B_RT_TXP_3

set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2B_RT_TXP_0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2B_RT_TXP_1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2B_RT_TXP_2
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to FPGA_XL2B_RT_TXP_3


# XCVR settings ############################################################################
if { $ETH_CONFIG == 0 } {
    post_message "#DEBUG_INFO: applied transceivers settings for 8x10G ETH_CONFIG"
#line side
    #RX 
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPA_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPA_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPA_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPB_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPB_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPB_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPB_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPA_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPA_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPA_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPB_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPB_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPB_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPB_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPB_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPB_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPB_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPB_RT_RXP_3
    #TX
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPB_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPB_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPB_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPB_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPB_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPB_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPB_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPB_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPB_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPB_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPB_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPB_RT_TXP_3
#host side
    #RX FVL0 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_3
    #RX FVL1 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_3
} elseif { $ETH_CONFIG == 1 } {
    post_message "#DEBUG_INFO: applied transceivers settings for 4x25G ETH_CONFIG"
#line side
    #RX 
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPA_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPA_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to QSFPA_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPA_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPA_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFPA_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_3
    #TX
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_3
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_2
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_3
#host side
    #RX FVL0 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_3
    #RX FVL0 ch1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_3        
    #RX FVL1 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_3    
    #RX FVL1 ch1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2B_RT_RXP_3    
} elseif { $ETH_CONFIG == 2 } {
    post_message "#DEBUG_INFO: applied transceivers settings for 2x1x25G ETH_CONFIG"
#line side
    #RX
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPB_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPB_RT_RXP_0
    #TX
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPB_RT_TXP_0
#host side
    #RX FVL0 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_3

    #RX FVL0 ch1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_3
} elseif { $ETH_CONFIG == 4 } {
    post_message "#DEBUG_INFO: applied transceivers settings for 2x2x25G ETH_CONFIG"
#line side
    #RX 
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPA_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPB_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPB_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPB_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPB_RT_RXP_1
    #TX
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPB_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPB_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPB_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPB_RT_TXP_1
#host side
    #RX FVL0 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_3
    #RX FVL0 ch1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1B_RT_RXP_3    
    
    #RX FVL1 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_3    
    #RX FVL1 ch1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2B_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2B_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2B_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2B_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2B_RT_RXP_3    
} elseif { $ETH_CONFIG == 5 } {
    post_message "#DEBUG_INFO: applied transceivers settings for 2x1x25G with 2 FVL ETH_CONFIG"
#line side
    #RX
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPB_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPB_RT_RXP_0
    #TX
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPB_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPB_RT_TXP_0
#host side
    #RX FVL0 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_3

    #RX FVL1 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_3    
} elseif { $ETH_CONFIG == 6 } {
    post_message "#DEBUG_INFO: applied transceivers settings for 1x2x25G ETH_CONFIG"
#line side
    #RX
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL RADP_CTLE_EQZ_1S_SEL_13 -to QSFPA_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to QSFPA_RT_RXP_1
    #TX
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 26 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 2 -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_NEG -to QSFPA_RT_TXP_1
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_0
    set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 0 -to QSFPA_RT_TXP_1
#host side
    #RX FVL0 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL1A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL1A_RT_RXP_3

    #RX FVL1 ch0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM STG1_GAIN7 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_4 -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to FPGA_XL2A_RT_RXP_3
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_0
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_1
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_2
    set_instance_assignment -name XCVR_A10_RX_EQ_BW_SEL EQ_BW_2 -to FPGA_XL2A_RT_RXP_3    
}
# FVL 40g backpressure pins ################################################################
set_location_assignment PIN_AU35 -to FPGA_XL1_ETH_BP0
set_location_assignment PIN_AU36 -to FPGA_XL1_ETH_BP1
set_location_assignment PIN_AV35 -to FPGA_XL2_ETH_BP0
set_location_assignment PIN_AV34 -to FPGA_XL2_ETH_BP1

set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_XL1_ETH_BP0
set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_XL1_ETH_BP1
set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_XL2_ETH_BP0
set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_XL2_ETH_BP1
# MDIO ######################################################################################
set_location_assignment PIN_BC33 -to FPGA_RTA_MDC
set_location_assignment PIN_BD33 -to FPGA_RTA_MDIO
set_location_assignment PIN_BA34 -to FPGA_RTB_MDC
set_location_assignment PIN_BB35 -to FPGA_RTB_MDIO

set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_RTA_MDC
set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_RTA_MDIO
set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_RTB_MDC
set_instance_assignment -name IO_STANDARD 1.8V -to FPGA_RTB_MDIO

set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_RTA_MDIO
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to FPGA_RTA_MDIO
set_instance_assignment -name SLEW_RATE 1 -to FPGA_RTA_MDIO

set_instance_assignment -name CURRENT_STRENGTH_NEW "STRENGTH 8MA" -to FPGA_RTB_MDIO
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to FPGA_RTB_MDIO
set_instance_assignment -name SLEW_RATE 1 -to FPGA_RTB_MDIO