Verilog实现串并转换
项目文件：
SIPO.zip
//------------------------------------------------------
// File Name : SIPO.v
// Author : ChanRa1n
// Description : A easy SIPO code
// Called by : TopModule
// Revision History : 2022-04-21
// Revision : 1.0
// Email : chenyu@myfpga.cn
// Copyright(c) 2018-Now, MYFPGA.CN, All right reserved.
//------------------------------------------------------
module SIPO (
input wire [0:0] Sys_clk,
input wire [0:0] Sys_rst_n,
input wire [0:0] Sig_si,
input wire [0:0] Sig_si_en,
output wire [7:0] Sig_po
);
reg [7:0] Sig_po_reg;
assign Sig_po = Sig_po_reg;
always@(posedge Sys_clk or negedge Sys_rst_n)begin
if(~Sys_rst_n)begin
Sig_po_reg <= 8'd0;
end
else begin
if(Sig_si_en)begin
Sig_po_reg <= {Sig_po_reg[6:0],Sig_si} ;
end
else begin
Sig_po_reg <= Sig_po_reg ;
end
end
end
endmodule
//------------------------------------------------------
// File Name : SIPO_TB.v
// Author : ChanRa1n
// Description : Testbench file for SIPO_TB
// Called by : Simulation
// Revision History : 2022-04-21
// Revision : 1.0
// Email : chenyu@myfpga.cn
// Copyright(c) 2018-Now, MYFPGA.CN, All right reserved.
//------------------------------------------------------
`default_nettype wire
`timescale 1ns/1ns
module SIPO_TB ();
reg Sys_clk;
reg Sys_rst_n;
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) Sys_clk=~Sys_clk;
reg [0:0] Sig_si;
reg [0:0] Sig_si_en;
wire [7:0] Sig_po;
SIPO SIPO (
.Sys_clk(Sys_clk),
.Sys_rst_n(Sys_rst_n),
.Sig_si(Sig_si),
.Sig_si_en(Sig_si_en),
.Sig_po(Sig_po)
);
initial begin
#1 Sys_rst_n<=1'b0;Sys_clk<=1'b0;
#(CLK_PERIOD*3) Sys_rst_n<=1;
repeat(100)begin
Sig_si <= {$random} % 2;
Sig_si_en <= {$random} % 2;
#(CLK_PERIOD);
end
$stop;
end
endmodule
