高速ADC模块开源页面 带Verilog示例程序
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ebit.pdfebit.PcbDoc...
//==========================================================================// Author : ChanRa1n// Description: Training for Intel FPGA/...
完整工程文件:clkdiv.zip//------------------------------------------------------// File Name : clkdiv.v// Author &nb...
`timescale 1ns / 1ps//-------------------------------------------------------//Filename ﹕ FIFO_TOP.v//Author ...
代码中的Sys_clk其实是没有用到的,项目文件:cdc_single.zip//------------------------------------------------------// File Name : cdc.v// Autho...